| Patent Number |
Title Of Patent |
Date Issued |
| 7374980 |
Field effect transistor with thin gate electrode and method of fabricating same |
May 20, 2008 |
| A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed |
| 7352025 |
Semiconductor memory device with increased node capacitance |
April 1, 2008 |
| An integrated circuit semiconductor memory device having the BOX layer removed from under the gate of a storage transistor to increase the gate-to-substrate capacitance and reduce the soft error rate. The increased node capacitance thus obtained is achieved without requiring a corres |
| 7341902 |
Finfet/trigate stress-memorization method |
March 11, 2008 |
| Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Sp |
| 7335932 |
Planar dual-gate field effect transistors (FETs) |
February 26, 2008 |
| A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region o |
| 7335563 |
Rotated field effect transistors and method of manufacture |
February 26, 2008 |
| An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substa |
| 7326976 |
Corner dominated trigate field effect transistor |
February 5, 2008 |
| Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the chann |
| 7309653 |
Method of forming damascene filament wires and the structure so formed |
December 18, 2007 |
| A method of forming a semiconductor device, and the device so formed. Depositing a low dielectric constant material on a substrate. Depositing a hard mask on the low dielectric constant material. Forming an at least one first feature within the low dielectric constant material and the |
| 7288445 |
Double gated transistor and method of fabrication |
October 30, 2007 |
| Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where on |
| 7285474 |
Air-gap insulated interconnections |
October 23, 2007 |
| Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending |
| 7274053 |
Fin device with capacitor integrated under gate electrode |
September 25, 2007 |
| A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel |
| 7259590 |
Driver for multi-voltage island/core architecture |
August 21, 2007 |
| A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regula |
| 7227205 |
Strained-silicon CMOS device and method |
June 5, 2007 |
| The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channe |
| 7205591 |
Pixel sensor cell having reduced pinning layer barrier potential and method thereof |
April 17, 2007 |
| A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinni |
| 7187042 |
Backgated FinFET having different oxide thicknesses |
March 6, 2007 |
| A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, |
| 7183573 |
Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet |
February 27, 2007 |
| A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor |
| 7132339 |
Transistor structure with thick recessed source/drain structures and fabrication process of same |
November 7, 2006 |
| An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a |
| 7105934 |
FinFET with low gate capacitance and low extrinsic resistance |
September 12, 2006 |
| A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin |
| 7102166 |
Hybrid orientation field effect transistors (FETs) |
September 5, 2006 |
| A hybrid orientation semiconductor structure and method of forming the same. The structure includes (a) a semiconductor substrate comprising a first semiconductor material having a first lattice orientation; (b) a back gate region on the semiconductor substrate; (c) a back gate diele |
| 7091128 |
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs |
August 15, 2006 |
| A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric b |
| 7087966 |
Double-Gate FETs (field effect transistors) |
August 8, 2006 |
| A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fi |
| 7075153 |
Grounded body SOI SRAM cell |
July 11, 2006 |
| A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, |
| 7056773 |
Backgated FinFET having different oxide thicknesses |
June 6, 2006 |
| A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, |
| 7009265 |
Low capacitance FET for operation at subthreshold voltages |
March 7, 2006 |
| A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1.times.10.sup.17/cc or 5.times.10.sup.16/cc and so tend to have a high resistance. The underlap regions reduce overlap ca |
| 6991979 |
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs |
January 31, 2006 |
| A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric b |
| 6960806 |
Double gated vertical transistor with different first and second gate materials |
November 1, 2005 |
| Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where on |
| 6947275 |
Fin capacitor |
September 20, 2005 |
| Disclosed is a capacitor structure and method for forming the same. This structure has a conductive substrate, conductive fins extending above the substrate, and trenches extending into the substrate. These trenches are positioned between locations where the fins extend above the substra |
| 6943405 |
Integrated circuit having pairs of parallel complementary FinFETs |
September 13, 2005 |
| A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel t |
| 6940130 |
Body contact MOSFET |
September 6, 2005 |
| A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the |
| 6913960 |
Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication |
July 5, 2005 |
| The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate an |
| 6870225 |
Transistor structure with thick recessed source/drain structures and fabrication process of same |
March 22, 2005 |
| An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a |
| 6867460 |
FinFET SRAM cell with chevron FinFET logic |
March 15, 2005 |
| An electronic device, and SRAM and a method of forming the electronic device and SRAM. The semiconductor device including: a pass gate transistor having a fin body having opposing sidewalls aligned in a first direction and having a first majority carrier mobility and a gate adjacent |
| 6774437 |
Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication |
August 10, 2004 |
| The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate an |
| 6774017 |
Method and structures for dual depth oxygen layers in silicon-on-insulator processes |
August 10, 2004 |
| A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the tre |
| 6677645 |
Body contact MOSFET |
January 13, 2004 |
| A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the |
| 6646305 |
Grounded body SOI SRAM cell |
November 11, 2003 |
| A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, |
| 6645789 |
On chip alpha-particle detector |
November 11, 2003 |
| An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said |
| 6624475 |
SOI low capacitance body contact |
September 23, 2003 |
| An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a seco |
| 6605981 |
Apparatus for biasing ultra-low voltage logic circuits |
August 12, 2003 |
| An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply an |
| 6552396 |
Matched transistors and methods for forming the same |
April 22, 2003 |
| An SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region |
| 6545330 |
On chip alpha-particle detector |
April 8, 2003 |
| An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said |
| 6512269 |
High-voltage high-speed SOI MOSFET |
January 28, 2003 |
| A semiconductor device including an SOI substrate; a plurality of diffusion regions in substrate, separated by, and abutting a plurality of body regions in said substrate, a first one of the body regions and its abutting diffusion regions having a first width and successive ones of the |
| 6498058 |
SOI pass-gate disturb solution |
December 24, 2002 |
| An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is |
| 6476445 |
Method and structures for dual depth oxygen layers in silicon-on-insulator processes |
November 5, 2002 |
| A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the tre |
| 6475838 |
Methods for forming decoupling capacitors |
November 5, 2002 |
| A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the |
| 6453431 |
System technique for detecting soft errors in statically coupled CMOS logic |
September 17, 2002 |
| Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for |
| 6437594 |
SOI pass gate leakage monitor |
August 20, 2002 |
| A monitor for detecting pass gate leakage in a silicon on insulator device and a method for using the same is described herein. A pulse generator supplies a signal to a set of buffers connected in parallel, which pass on a signal to the source side of a series of NFETs. The plurality of |
| 6436744 |
Method and structure for creating high density buried contact for use with SOI processes for hig |
August 20, 2002 |
| A semiconductor device having an SOI FET comprising a silicon body on an insulating layer on a conductive substrate. A gate dielectric and a gate are provided on a surface of the silicon body, and a source and a drain are provided on two sides of the gate. A buried body contact to the |
| 6404236 |
Domino logic circuit having multiplicity of gate dielectric thicknesses |
June 11, 2002 |
| A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is |
| 6400171 |
Method and system for processing integrated circuits |
June 4, 2002 |
| A circuit and a method for automatically detecting an operating condition of an integrated circuit chip and for automatically outputting a control signal in response to automatically detecting one of at least two said operating conditions. With the preferred embodiment, FET off currents |
| 6368903 |
SOI low capacitance body contact |
April 9, 2002 |
| An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a seco |
