| Patent Number |
Title Of Patent |
Date Issued |
| 7423336 |
Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and |
September 9, 2008 |
| A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerou |
| 7375419 |
Stacked mass storage flash memory package |
May 20, 2008 |
| A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dic |
| 7372138 |
Routing element for use in multi-chip modules, multi-chip modules including the routing element |
May 13, 2008 |
| A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a carrier substrate of the semiconductor device assembly. The conductive |
| 7372131 |
Routing element for use in semiconductor device assemblies |
May 13, 2008 |
| A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a carrier substrate of the semiconductor device assembly. The conductive |
| 7321160 |
Multi-part lead frame |
January 22, 2008 |
| A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor devi |
| 7282805 |
Bond pad rerouting element and stacked semiconductor device assemblies including the rerouting e |
October 16, 2007 |
| A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting |
| 7282397 |
Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemb |
October 16, 2007 |
| A rerouting element for a semiconductor device includes a substantially planar member that carries at least one contact location, at least one conductive, at least one rerouted bond pad. The contact location is positioned adjacent to a first periphered edge of the substantially plana |
| 7268013 |
Method of fabricating a semiconductor die package having improved inductance characteristics |
September 11, 2007 |
| A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive |
| 7262506 |
Stacked mass storage flash memory package |
August 28, 2007 |
| A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dic |
| 7232747 |
Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formatio |
June 19, 2007 |
| A method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the wafer in at least one electroless bath having a nickel-containing solution therein, wherein bumps having a nickel-containi |
| 7227261 |
Vertical surface mount assembly and methods |
June 5, 2007 |
| A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. At least a portion of the |
| 7125749 |
Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC pac |
October 24, 2006 |
| An integrated circuit package includes a package body, such as a transfer molded plastic or preformed ceramic package body, having an integrated circuit die positioned therein. A lead frame, such as a peripheral lead, Leads-Over-Chip (LOC), or Leads-Under-Chip (LUC) lead frame, includes |
| 7112252 |
Assembly method for semiconductor die and lead frame |
September 26, 2006 |
| A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active |
| 7098527 |
Integrated circuit package electrical enhancement with improved lead frame design |
August 29, 2006 |
| A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilize |
| 7094631 |
Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemb |
August 22, 2006 |
| A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerou |
| 7091061 |
Method of forming a stack of packaged memory dice |
August 15, 2006 |
| A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit se |
| 7084514 |
Multi-chip module and methods |
August 1, 2006 |
| A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. |
| 7061092 |
High-density modularity for ICS |
June 13, 2006 |
| A high-density multi-chip module and method for construction thereof, wherein a plurality of integrated circuit dice with at least one row of generally central bond pads is bonded in a staggered flip-chip style to opposite sides of a metallized substrate. The bond pads of each die are |
| 7038315 |
Semiconductor chip package |
May 2, 2006 |
| A semiconductor chip package that includes discrete conductive leads in electrical contact with bond pads on a semiconductor chip. This chip/lead assembly is encapsulated within an encapsulating material and electrode bumps are formed through the encapsulating material to contact the |
| 6995043 |
Methods for fabricating routing elements for multichip modules |
February 7, 2006 |
| A routing element for use with a multichip module that includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a multichip module substrate. The conductive traces may be carried upon a sing |
| 6987325 |
Bond pad rerouting element and stacked semiconductor device assemblies including the rerouting e |
January 17, 2006 |
| A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerou |
| 6982486 |
Cavity ball grid array apparatus having improved inductance characteristics and method of fabric |
January 3, 2006 |
| A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive |
| 6979904 |
Integrated circuit package having reduced interconnects |
December 27, 2005 |
| A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate |
| 6979895 |
Semiconductor assembly of stacked substrates and multiple semiconductor dice |
December 27, 2005 |
| A semiconductor package comprising multiple stacked substrates having flip-chips attached to the substrates with chip-on-board assembly techniques to achieve dense packaging. The substrates are preferably stacked atop one another by electric connections which are column-like structur |
| 6979596 |
Method of fabricating a tape having apertures under a lead frame for conventional IC packages |
December 27, 2005 |
| A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is |
| 6965160 |
Semiconductor dice packages employing at least one redistribution layer |
November 15, 2005 |
| A method and apparatus for assembling and packaging semiconductor dice. The semiconductor dice or assemblies of stacked and electrically interconnected semiconductor dice are placed at mutually spaced locations with respect to a common plane and encapsulated in a dielectric material |
| 6946722 |
Multi-part lead frame with dissimilar materials |
September 20, 2005 |
| A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device |
| 6921966 |
Tape under frame for lead frame IC package assembly |
July 26, 2005 |
| A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is |
| 6906409 |
Multichip semiconductor package |
June 14, 2005 |
| A multichip semiconductor package and method of making is provided that has a plurality of semiconductor chips fabricated in electrical isolation one from another integrally on a singular coextensive substrate useful for numerous and varied semiconductor chip applications. The semiconduc |
| 6902952 |
Multi-part lead frame with dissimilar materials and method of manufacturing |
June 7, 2005 |
| A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment d |
| 6900549 |
Semiconductor assembly without adhesive fillets |
May 31, 2005 |
| Disclosed is a method for forming a semiconductor assembly and the resulting assembly in which a flowable adhesive material which secures a die to a support and does not form an adhesive fillet. A flowable adhesive is deposited between the die and support so that it covers about 50 to |
| 6900528 |
Stacked mass storage flash memory package |
May 31, 2005 |
| A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dic |
| 6897553 |
Apparatus for forming a stack of packaged memory dice |
May 24, 2005 |
| A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit se |
| 6897096 |
Method of packaging semiconductor dice employing at least one redistribution layer |
May 24, 2005 |
| A method and apparatus for assembling and packaging semiconductor dice. The semiconductor dice or assemblies of stacked and electrically interconnected semiconductor dice are placed at mutually spaced locations with respect to a common plane and encapsulated in a dielectric material |
| 6894372 |
Tape under frame for lead frame IC package assembly |
May 17, 2005 |
| A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is |
| 6884654 |
Method of forming a stack of packaged memory dice |
April 26, 2005 |
| A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit se |
| 6882034 |
Routing element for use in multi-chip modules, multi-chip modules including the routing element, |
April 19, 2005 |
| A routing element for use with a multichip module includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths that those provided by a multichip module substrate. The conductive traces may be carried upon a single surfac |
| 6867500 |
Multi-chip module and methods |
March 15, 2005 |
| A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region, but within the second region |
| 6837731 |
Locking assembly for securing a semiconductor device to a carrier substrate |
January 4, 2005 |
| A semiconductor package for vertically surface mounting to a printed circuit board having a retention apparatus for holding the package thereto. |
| 6831353 |
Interdigitated leads-over-chip lead frame and device for supporting an integrated circuit die |
December 14, 2004 |
| An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least |
| 6815251 |
High density modularity for IC's |
November 9, 2004 |
| A high density multi-chip module and method for construction thereof, wherein a plurality of integrated circuit dice with at least one row of generally central bond pads is bonded in a staggered flip-chip style to opposite sides of a metallized substrate. The bond pads of each die are |
| 6781839 |
Vertical surface mount apparatus with thermal carrier and method |
August 24, 2004 |
| A high density vertical surface mount package and thermal carrier therefore including a heat sink. |
| 6773955 |
Low profile multi-IC chip package connector |
August 10, 2004 |
| A low profile multi-IC chip package for high-speed applications comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with |
| 6747344 |
Lead frame assemblies with voltage reference plane and IC packages including same |
June 8, 2004 |
| A semiconductor die assembly employing a voltage reference plane structure electrically isolated from, but in immediate proximity to, leads of a lead frame to which the die is electrically connected. A non-conductive adhesive or an adhesively-coated dielectric film is used to position th |
| 6740971 |
Cavity ball grid array apparatus having improved inductance characteristics |
May 25, 2004 |
| A ball grid array (BGA) package includes a central cavity for receiving a semiconductor die therein. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically-conductive adhesive layer. Bond p |
| 6738263 |
Stackable ball grid array package |
May 18, 2004 |
| A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, |
| 6737734 |
Structure and method for securing bussing leads |
May 18, 2004 |
| A hybrid lead frame having leads for conventional lead-to-I/O wire bonding, and leads for power and ground bussing that extend over a surface of the semiconductor die are provided where the leads for bussing are held in place by lead-lock tape to prevent bending and/or other movement of |
| 6686655 |
Low profile multi-IC chip package connector |
February 3, 2004 |
| A low profile multi-IC chip package for high-speed applications comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with |
| 6677671 |
Apparatus for forming a stack of packaged memory dice |
January 13, 2004 |
| A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit se |
| 6670702 |
Stackable ball grid array package |
December 30, 2003 |
| A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, |
