| Patent Number |
Title Of Patent |
Date Issued |
| 7427775 |
Fabricating strained channel epitaxial source/drain transistors |
September 23, 2008 |
| The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline fi |
| 7365375 |
Organic-framework zeolite interlayer dielectrics |
April 29, 2008 |
| An organic-framework zeolite interlayer dielectric is disclosed. The interlayer dielectric's resistance to chemical attack, its dielectric constant, its mechanical strength, or combinations thereof can be tailored by (1) varying the ratio of carbon-to-oxygen in the organic-framework |
| 7335586 |
Sealing porous dielectric material using plasma-induced surface polymerization |
February 26, 2008 |
| A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectri |
| 7303989 |
Using zeolites to improve the mechanical strength of low-k interlayer dielectrics |
December 4, 2007 |
| A method for impregnating the pores of a zeolite low-k dielectric layer with a polymer, and forming an interconnect structure therein, thus mechanically strengthening the dielectric layer and preventing metal deposits within the pores. |
| 7274055 |
Method for improving transistor performance through reducing the salicide interface resistance |
September 25, 2007 |
| An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regio |
| 7226842 |
Fabricating strained channel epitaxial source/drain transistors |
June 5, 2007 |
| The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline fi |
| 7223679 |
Transistor gate electrode having conductor material layer |
May 29, 2007 |
| Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work |
| 7220668 |
Method of patterning a porous dielectric material |
May 22, 2007 |
| A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conduc |
| 7179755 |
Forming a porous dielectric layer and structures formed thereby |
February 20, 2007 |
| Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the |
| 6974733 |
Double-gate transistor with enhanced carrier mobility |
December 13, 2005 |
| There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel. |
| 6949482 |
Method for improving transistor performance through reducing the salicide interface resistance |
September 27, 2005 |
| An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regio |
| 6933589 |
Method of making a semiconductor transistor |
August 23, 2005 |
| Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wher |
| 6812086 |
Method of making a semiconductor transistor |
November 2, 2004 |
| Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wher |
| 6746967 |
Etching metal using sonication |
June 8, 2004 |
| A technique in accordance with the invention includes obtaining a semiconductor structure that has a metal disposed thereon. At least a portion of the metal is etched using an etching fluid while sonic energy is applied to the etching fluid. |
| 6723622 |
Method of forming a germanium film on a semiconductor substrate that includes the formation of a |
April 20, 2004 |
| A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas |
| 6703291 |
Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions |
March 9, 2004 |
| The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, |
