| Patent Number |
Title Of Patent |
Date Issued |
| 7422926 |
Self-aligned process for manufacturing phase change memory cells |
September 9, 2008 |
| A process for manufacturing phase change memory cells includes the step of forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with the heater element. In order to form the heater element and the phase change storage region |
| 7372166 |
Sublithographic contact structure, phase change memory cell with optimized heater shape, and man |
May 13, 2008 |
| An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the |
| 7307451 |
Field programmable gate array device |
December 11, 2007 |
| The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch |
| 7259040 |
Process for manufacturing a phase change memory array in Cu-damascene technology and phase chang |
August 21, 2007 |
| A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a res |
| 7227765 |
Content addressable memory cell |
June 5, 2007 |
| A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for |
| 7227171 |
Small area contact region, high efficiency phase change memory cell and fabrication method there |
June 5, 2007 |
| A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first |
| 7176553 |
Integrated resistive elements with silicidation protection |
February 13, 2007 |
| In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity is then formed in the active area (15). |
| 7135756 |
Array of cells including a selection bipolar transistor and fabrication method thereof |
November 14, 2006 |
| A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a pluralit |
| 7110289 |
Method and system for controlling MRAM write current to reduce power consumption |
September 19, 2006 |
| In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at s |
| 7012832 |
Magnetic memory cell with plural read transistors |
March 14, 2006 |
| A magnetic random access memory (MRAM) device has increased .DELTA.R/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying r |
| 6974734 |
Process for manufacturing a memory device, in particular a phase change memory, including a sili |
December 13, 2005 |
| A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the |
| 6972430 |
Sublithographic contact structure, phase change memory cell with optimized heater shape, and man |
December 6, 2005 |
| An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the wall |
| 6891747 |
Phase change memory cell and manufacturing method thereof using minitrenches |
May 10, 2005 |
| The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second |
| 6750505 |
Non-volatile memory cell with floating gate region autoaligned to the isolation and with a high |
June 15, 2004 |
| A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade |
| 6734490 |
Nonvolatile memory cell with high programming efficiency |
May 11, 2004 |
| The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in th |
| 6567296 |
Memory device |
May 20, 2003 |
| A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each secon |
| 6537879 |
Process for manufacturing a non-volatile memory cell with a floating gate region autoaligned to |
March 25, 2003 |
| A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade |
| 6294431 |
Process of manufacture of a non-volatile memory with electric continuity of the common source li |
September 25, 2001 |
| A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said proces |
| 6222245 |
High capacity capacitor and corresponding manufacturing process |
April 24, 2001 |
| The invention relates to a high-capacitance capacitor which is monolithically integratable on a semiconductor substrate doped with a first type of dopant and accommodating a diffusion well which is doped with a second type of dopant and has a first active region formed therein.A layer of |
| 6071778 |
Memory device with a memory cell array in triple well, and related manufacturing process |
June 6, 2000 |
| A memory device comprising a semiconductor material substrate with a dopant of a first type; a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in said first well; an arra |
| 5990526 |
Memory device with a cell array in triple well, and related manufacturing process |
November 23, 1999 |
| A memory device comprising a semiconductor material substrate with a dopant of a first type, a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in the first well, an array |
| 5784319 |
Method for erasing an electrically programmable and erasable non-volatile memory cell |
July 21, 1998 |
| A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode. The method provides for coupling the control electrode to a first voltage supply and coupling the first elect |
