| Patent Number |
Title Of Patent |
Date Issued |
| 7088627 |
Column redundancy scheme for non-volatile flash memory using JTAG input protocol |
August 8, 2006 |
| A JTAG-programmable IC includes a memory array having redundant columns, a partial-width data register, and a full-width bitline register. A programming bitstream is shifted into the data register in discrete portions, with each portion being loaded into the bitline latch before the |
| 6861895 |
High voltage regulation circuit to minimize voltage overshoot |
March 1, 2005 |
| A resistive divider for a voltage multiplier circuit minimizes output voltage overshoot by capacitively coupling the tap point of the resistive divider to the output terminal of the voltage multiplier circuit via the parasitic capacitance of the resistive divider. For a resistive divider |
| 6816420 |
Column redundancy scheme for serially programmable integrated circuits |
November 9, 2004 |
| A serially programmable integrated circuit (IC) includes a memory array and multiple data registers daisy-chained by bypass logic. Each of the data registers is associated with a primary column grouping or redundant column grouping in the memory array. If a data register is associated wi |
| 5991194 |
Method and apparatus for providing accessible device information in digital memory devices |
November 23, 1999 |
| A memory device (100) includes a user device information sector (122) in addition to normal sectors (124) of a memory array. The user device information sector includes a product identification field (240) and a restricted address list field (250), and optionally includes a customer |
| 5862099 |
Non-volatile programmable memory having a buffering capability and method of operation thereof |
January 19, 1999 |
| A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the |
| 5724303 |
Non-volatile programmable memory having an SRAM capability |
March 3, 1998 |
| A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustrtively a serial device connected to the serail port of the microcontrollerThe memory device includes a page latch load circuit which provides serial I/O to the mic |
| 5313429 |
Memory circuit with pumped voltage for erase and program operations |
May 17, 1994 |
| A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operation |
| 5216588 |
Charge pump with high output current |
June 1, 1993 |
| A charge pump circuit is disclosed that enables the conversion of a low voltage to a higher voltage while delivering a substantial amount of current. The charge pump circuit includes a plurality of diode-capacitor voltage multiplier pump units connected in parallel with respect to each |
