| Patent Number |
Title Of Patent |
Date Issued |
| 7385844 |
Semiconductor device and method of controlling the same |
June 10, 2008 |
| A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a W |
| 7372743 |
Controlling a nonvolatile storage device |
May 13, 2008 |
| A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation |
| 7362620 |
Semiconductor device and method of controlling the same |
April 22, 2008 |
| A semiconductor device (1) includes a non-volatile memory cell array (2), a write/read circuit (30) writing data into and reading data from the non-volatile memory cell array (2), a data input/output circuit (80), and a volatile memory cell array (40) including a first latch circuit (41) |
| 7321511 |
Semiconductor device and method for controlling operation thereof |
January 22, 2008 |
| A semiconductor device includes a semiconductor substrate, word lines, global bit lines, and inversion gates that form inversion layers serving as local bit lines in the semiconductor substrate. The inversion layers are electrically connected to the global bit lines and a memory cell use |
| 7274602 |
Storage device and control method therefor |
September 25, 2007 |
| The conductance of a first switch circuit (T1) is periodically controlled in response to an error-amplification circuit (A1) whereby electric power, stored in an inductance circuit (L1) from INPUT VOLTAGE VIN, is released, through a rectifier circuit (D1), to a memory cell array (11) |
| 7151293 |
SONOS memory with inversion bit-lines |
December 19, 2006 |
| A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory |
| 7096406 |
Memory controller for multilevel cell memory |
August 22, 2006 |
| A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is |
| 6385088 |
Non-volatile memory device |
May 7, 2002 |
| A non-volatile memory device including a plurality of block, each including: a main bit line; a plurality of sub-bit lines to which memory transistors are connected and which are arranged in parallel with respect to the main bit line; and two cascade-connected selection gates which are |
| 6208200 |
Level shift circuit with low voltage operation |
March 27, 2001 |
| A level shift circuit capable of performing a low voltage operation without increasing the power consumption is described. A charge pump type level shift circuit incorporates NMOS transistors having well-in-well structures, where the potential of these wells are designed to rise along |
| 5883501 |
Power supply circuit |
March 16, 1999 |
| A power supply circuit provided with an operation control circuit to control the operation of an oscillator, a comparator, and a reference voltage generator by generating a pump enable signal. During normal operation, the operation control circuit generates an active pump enable sign |
| 5590073 |
Random access memory having flash memory |
December 31, 1996 |
| A semiconductor nonvolatile memory device including first and second bit lines, a buffer memory connected to the first and second bit lines, an electrically erasable programmable nonvolatile memory connected to the first and second bit lines, a writing latch circuit to which the first an |
| 5489870 |
Voltage booster circuit |
February 6, 1996 |
| A booster circuit which can cancel the back bias effect, can prevent the increase of the surface area of the circuit and the power consumption, prevent the complication of the clock generation circuit, and prevent lowering of the current capability, wherein a boosting stage is consti |
| 5459694 |
Nonvolatile storage apparatus with folded bit line structure |
October 17, 1995 |
| A semiconductor nonvolatile memory device which can adopt a folded bit line system and can achieve an enhancement of speed of the read out time etc., which device adopting a differential type sensing system comprising a bit line BL and an inverted bit line BL.sub.-- connected in paralle |
| 5396459 |
Single transistor flash electrically programmable memory cell in which a negative voltage is app |
March 7, 1995 |
| A nonvolatile semiconductor memory using a single floating gate transistor, wherein a control gate elecrrode is negatively biased while a source region is positively biased, and a writing operation is performed bit by bit by transferring electrons from the floating gate into the source |
| 5388078 |
Semiconductor memory device having current to voltage conversion type amplifier |
February 7, 1995 |
| A semiconductor memory device of the present invention includes a sense amplifier for converting an electrical current flowing through a sense node between a load and a current limiting circuit into an electrical voltage and for outputting the produced electrical voltage. The sense a |
| 5253200 |
Electrically erasable and programmable read only memory using stacked-gate cell |
October 12, 1993 |
| An electrically erasable programmable nonvolatile memory device includes a plurality of memory cells. The memory device has architecture similar to or the same as an UV-EPROM. Erasure operating is performed by applying a negative voltage to a control gate so as to inject holes into the f |
| 5198997 |
Ultraviolet erasable nonvolatile memory with current mirror circuit type sense amplifier |
March 30, 1993 |
| An ultraviolet erasable nonvolatile memory device comprising a plurality of memory cells which are erasable by ultraviolet rays employs a sense amplifier consisting a current mirror circuit. The current mirror circuit is connected to the memory cells and a reference cell respectively for |
| 5189641 |
Non-volatile random access memory device |
February 23, 1993 |
| A semiconductor memory device includes a memory cell including a volatile memory cell portion having a flip-flop and a non-volatile memory cell portion individually and respectively associated with the volatile memory cell portion and including a capacitor portion operatively connected t |
| 5136541 |
Programmable read only memory using stacked-gate cell erasable by hole injection |
August 4, 1992 |
| An electrically erasable programmable nonvolatile memory device includes a plurality of memory cells. The memory device has architecture similar to or same as an UV-EPROM. Erasure operating is performed by applying negative voltage to a control gate so as to inject holes into the floatin |
| 5099143 |
Dual voltage supply circuit with multiplier-controlled transistor |
March 24, 1992 |
| An address decoder circuit adapted for enabling electrical erasure in a non-volatile memory without the necessity of numerically increasing the component elements, wherein the direction of application (polarity) of a supply voltage during an erasing operation to a decoding logic gate |
| 5051958 |
Nonvolatile static memory device utilizing separate power supplies |
September 24, 1991 |
| A semiconductor nonvolatile memory device includes a static type RAM constituted by a flip-flop circuit having a pair of loads, each load being supplied by separate power sources. An electrically erasable programmable ROM is constituted by a nonvolatile memory transistor operatively |
| 5039882 |
Address decoder circuit for non-volatile memory |
August 13, 1991 |
| An address decoder circuit adapted for enabling electrical erasure in a non-volatile memory without the necessity of numerically increasing the component elements, wherein the direction of application (polarity) of a supply voltage during an erasing operation to a decoding logic gate |
| 5029132 |
Random access memory device having parallel non-volatile memory cells |
July 2, 1991 |
| A non-volatile random access memory device comprising a plurality of memory cells, each of the memory cells comprising, a volatile memory cell and a pair of non-volatile memory cells connected to the volatile memory cell for storing data from the volatile memory cell and for recalling th |
| 4878203 |
Semiconductor non-volatile memory with cut-off circuit when leakage occurs |
October 31, 1989 |
| A semiconductor non-volatile memory device includes: a memory cell array having a plurality of memory cells, each including a non-volatile memory cell portion; a high voltage generating circuit for generating a high voltage required for storing data; a plurality of high voltage wirings, |
| 4817055 |
Semiconductor memory circuit including bias voltage generator |
March 28, 1989 |
| A semiconductor memory circuit includes therein a bias voltage generator which produces a bias voltage to be supplied to a control gate of a field effect transistor (FET) which forms a part of each memory cell in the semiconductor memory circuit. The bias voltage generator is comprised o |
| 4800533 |
Semiconductor nonvolatile memory device |
January 24, 1989 |
| A semiconductor nonvolatile memory device includes a plurality of nonvolatile random access memory cells constituted by volatile memory cells and nonvolatile erasable programmable read only memory cells. A sense circuit senses a level of potential of a power source, and based on the |
| 4799194 |
Semiconductor random access nonvolatile memory device with restore and control circuits |
January 17, 1989 |
| In a nonvolatile memory device which is integrated by combining SRAM cells and nonvolatile memory cells at a ratio of 1:1; a control circuit is provided which, at a recall time, selects all word lines and supplies a predetermined electric potential to bit lines, so that a recall is carri |
| 4791614 |
Semiconductor memory device having erroneous write operation preventing function |
December 13, 1988 |
| In a semiconductor memory device such as an E.sup.2 PROM, a write enable signal (WE) is supplied to a buffer formed by an enhancement-type transistor (Q.sub.11) and a depletion-type transistor (Q.sub.12) having a node (N.sub.3). The potential at this node is applied to a set terminal of |
| 4744058 |
Semiconductor programmable memory device and method of writing a predetermined pattern to same |
May 10, 1988 |
| A semiconductor programmable memory device, especially an E.sup.2 PROM, in which a checkerboard pattern for testing the operation of the memory matrix is easily written. The E.sup.2 PROM is provided with a circuit which can select all of the word lines or every other word line at the |
| 4703456 |
Non-volatile random access memory cell |
October 27, 1987 |
| A non-volatile random access memory (NVRAM) cell including a volatile static type random access memory cell consisting of a flop-flip circuit having two nodes on which a paired bit signal are accessed and a non-volatile electrically erasable programmable read-only memory (EEPROM) cel |
| 4703196 |
High voltage precharging circuit |
October 27, 1987 |
| A precharging circuit employing ordinary enhancement (E) types MIST'S produces erasing and writing (E-W) voltages to change the data stored in an EEPROM fabricated in a common memory chip with the circuit. The E-W voltage increases gradually from a low level to a high level over a long |
| 4699690 |
Method of producing semiconductor memory device |
October 13, 1987 |
| A method of producing a semiconductor memory device comprises the steps of forming a first mask on a substrate and forming an opening in the first mask, implanting impurity ions into the substrate from the opening in the first mask so as to form an impurity region, forming a side wall la |
| 4682051 |
Voltage level detection circuit |
July 21, 1987 |
| A voltage level detection circuit connected between first and second feed lines, including a first depletion-type metal insulator semiconductor (MIS) transistor connected between the first feed line and a common node and having a gate connected to the first feed line, a second deplet |
| 4677590 |
Nonvolatile semiconductor memory circuit including dummy sense amplifiers |
June 30, 1987 |
| A nonvolatile semiconductor memory circuit is provided with a plurality of bit lines and a plurality of word lines. The nonvolatile semiconductor memory cells are located at intersections of the bit lines and word lines and formed by MOS transistors having a floating gate and a control g |
| 4644182 |
Delay circuit having delay time period determined by discharging operation |
February 17, 1987 |
| A delay circuit including: a P-channel enhancement-type transistor (Q.sub.11), linked between an input terminal (IN) and an output terminal (OUT); a capacitor (C) connected to the gate of the transistor (Q.sub.11); a charging switch (SW.sub.1) for charging the capacitor (C); a dischargin |
| 4636658 |
Voltage detecting device |
January 13, 1987 |
| A voltage detecting device including a voltage dividing circuit (VD) formed by two capacitors (C.sub.1 ', C.sub.2) connected in series, an inverter circuit (INV) for detecting whether the potential at the common node (N.sub.1) of the capacitors (C.sub.1 ', C.sub.2) reaches a predetermine |
| 4630238 |
Semiconductor memory device |
December 16, 1986 |
| A semiconductor memory device including a nonvolatile random access memory cell constituted by a combination of a static random access memory cell or a dynamic random access memory cell and a floating circuit element, is disclosed.In the device, the circuit constitution, the application |
| 4601020 |
Semiconductor memory device |
July 15, 1986 |
| An EEPROM utilizing a tunneling electron for writing and/or erasing, has charge pump circuits for pumping charge onto selected column and row lines up to a high voltage. In each of the charge pump circuits, a transistor is provided for intercepting clock pulses applied to a capacitor in |
| 4584494 |
Semiconductor timer |
April 22, 1986 |
| A semiconductor timer has a first MOS capacitor, a charge circuit for charging the first MOS capacitor, and a discharge circuit for discharging the first MOS capacitor. At least one of the charge and discharge circuits includes a transistor connected to the first MOS capacitor in series, |
| 4503519 |
Semiconductor non-volatile memory element of an electrically erasable type |
March 5, 1985 |
| A semiconductor non-volatile memory element of an electrically erasable type includes a floating gate formed on a semiconductor substrate through a first insulating film, and an erase-only or a write/erase gate formed through a second insulating film on the floating gate. The second |
| 4479126 |
MIS Decoder circuit |
October 23, 1984 |
| A decoder circuit, used, for example, in a semiconductor memory device, decodes an n bit address signal and selects one of 2.sup.n output lines such as word lines or bit lines. In the decoder circuit, MIS transistors connected to decoded signal output lines are commonly used by adjacent |
| 4402064 |
Nonvolatile memory |
August 30, 1983 |
| A nonvolatile memory, especially an electrically erasable and programmable read only memory (EE-PROM) includes an array of memory cells. In each of the memory cells four transistors are formed, that is a read transistor and a first selecting transistor connected in series, and a write-er |
| 4368524 |
Semiconductor device |
January 11, 1983 |
| A semiconductor device for comprising electrically alterable read-only memories formed in and on the same silicon substrate is disclosed. The read-only memories are driven by both a first voltage having one polarity and a second voltage having the opposite polarity. The first voltage is |
| 4355375 |
Semiconductor memory device |
October 19, 1982 |
| A semiconductor memory device includes a plurality of floating gate transistors each of which comprises a semiconductor substrate, a first and second impurity doped region, channel region formed between the first and second impurity doped regions, a floating gate electrode formed on the |
| 4298629 |
Method for forming a nitride insulating film on a silicon semiconductor substrate surface by dir |
November 3, 1981 |
| In a method for forming an insulating film on a semiconductor substrate surface, the silicon nitride of the insulating film has been formed by a plasma CVD or a direct nitridation. In the present invention, a gas plasma of a nitrogen-containing gas is generated in a direct nitridation re |
