| Patent Number |
Title Of Patent |
Date Issued |
| 7404126 |
Scan tests tolerant to indeterminate states when employing signature analysis to analyze test ou |
July 22, 2008 |
| Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. |
| 7352169 |
Testing components of I/O paths of an integrated circuit |
April 1, 2008 |
| Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell |
| 7082558 |
Increasing possible test patterns which can be used with sequential scanning techniques to perfo |
July 25, 2006 |
| A non-robust test pattern, which causes a transition on a path of interest as well as off-paths, may be selected as being suitable for performing delay analysis of the path of interest (e.g., critical path) if the transitions caused on the off-paths would not overlap with the transition |
| 6981190 |
Controlling the content of specific desired memory elements when testing integrated circuits usi |
December 27, 2005 |
| A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test pattern generation (ATPG)). The launch multiplexor may be employed in addition to a scan multiplexor, which enables the test pattern |
| 6853212 |
Gated scan output flip-flop |
February 8, 2005 |
| A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed. The scan output buffer i |
