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John Robert Abernathey Patents
Inventor:
Abernathey; John Robert
Address:
Underhill, VT
No. of patents:
1
Patents:




Patent Number Title Of Patent Date Issued
5672901 Structure for interconnecting different polysilicon zones on semiconductor substrates for integr September 30, 1997
A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which


 
 
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