| Patent Number |
Title Of Patent |
Date Issued |
| 5453400 |
Method and structure for interconnecting different polysilicon zones on semiconductor substrates |
September 26, 1995 |
| A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which |
| 5219788 |
Bilayer metallization cap for photolithography |
June 15, 1993 |
| A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier |
| 4755478 |
Method of forming metal-strapped polysilicon gate electrode for FET device |
July 5, 1988 |
| A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes |
| 4725560 |
Silicon oxynitride storage node dielectric |
February 16, 1988 |
| An annealing process carried out at 800.degree. C. in a wet O.sub.2 ambient permits the manufacture of a reliable storage capacitor wherein the dielectric layer is comprised of silicon oxynitride formed by low pressure chemical vapor deposition (LPCVD). The manufacturing process includes |
| 4649627 |
Method of fabricating silicon-on-insulator transistors with a shared element |
March 17, 1987 |
| A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate regi |
| 4601779 |
Method of producing a thin silicon-on-insulator layer |
July 22, 1986 |
| A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown |
| 4556585 |
Vertically isolated complementary transistors |
December 3, 1985 |
| A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated wit |
