| Patent Number |
Title Of Patent |
Date Issued |
| 7314830 |
Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt |
January 1, 2008 |
| A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at |
| 7314805 |
Method for fabricating semiconductor device |
January 1, 2008 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 7214577 |
Method of fabricating semiconductor integrated circuit device |
May 8, 2007 |
| A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at |
| 7118983 |
Method of fabricating semiconductor device |
October 10, 2006 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 7094655 |
Method of fabricating semiconductor device |
August 22, 2006 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 7094642 |
Method of fabricating semiconductor device |
August 22, 2006 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 7074665 |
Method of fabricating semiconductor device |
July 11, 2006 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 7064040 |
Method of fabricating semiconductor device |
June 20, 2006 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 6989600 |
Integrated circuit device having reduced substrate size and a method for manufacturing the same |
January 24, 2006 |
| CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on |
| 6861344 |
Method of manufacturing a semiconductor integrated circuit device |
March 1, 2005 |
| The corrosion of a pad portion on TEG is prevented, and the wettability of a solder and the shear strength after solder formation of a pad portion of an actual device are improved. A third layer wiring M3 on a chip area CA of a semiconductor wafer and a third layer wiring M3 on a scribe |
| 6858484 |
Method of fabricating semiconductor integrated circuit device |
February 22, 2005 |
| A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at |
| 6780757 |
Semiconductor integrated circuit device and method for making the same |
August 24, 2004 |
| A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the t |
| 6693001 |
Process for producing semiconductor integrated circuit device |
February 17, 2004 |
| A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at |
| 6670251 |
Method of fabricating semiconductor device |
December 30, 2003 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 6610564 |
Method of fabricating semiconductor device |
August 26, 2003 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 6583049 |
Semiconductor integrated circuit device and method for making the same |
June 24, 2003 |
| A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the t |
| 6545326 |
Method of fabricating semiconductor device |
April 8, 2003 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
| 6538329 |
Semiconductor integrated circuit device and method for making the same |
March 25, 2003 |
| A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the t |
| 6503803 |
Method of fabricating a semiconductor integrated circuit device for connecting semiconductor reg |
January 7, 2003 |
| Disclosed is a method of fabricating a semiconductor device including forming an insulating film on a silicon substrate; forming a contact hole in the insulating film; depositing a titanium film to be in contact with the silicon substrate in the contact hole; and causing a heat reaction |
| 6300237 |
Semiconductor integrated circuit device and method for making the same |
October 9, 2001 |
| A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the t |
| 6300206 |
Method for manufacturing semiconductor device |
October 9, 2001 |
| A implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the s |
| 6268658 |
Semiconductor integrated circuit device for connecting semiconductor region and electrical wirin |
July 31, 2001 |
| A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titan |
| 6031288 |
Semiconductor integrated circuit device for connecting semiconductor region and electrical wirin |
February 29, 2000 |
| A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titan |
| 5904556 |
Method for making semiconductor integrated circuit device having interconnection structure using |
May 18, 1999 |
| A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the t |
| 5453760 |
Position detecting apparatus |
September 26, 1995 |
| A position detecting apparatus is provided with a detecting face so as to detect the positions of points specified on the detection face thereof, which is capable of the detection of the minute position with a detection resolution for the whole detection face being not made finer, becaus |
