| Patent Number |
Title Of Patent |
Date Issued |
| 5511170 |
Digital bus data retention |
April 23, 1996 |
| A digital bus is driven to the logic state of a data input signal upon activating a data enable signal. A bus keeper enable signal activates a buffer having its input and output connected to the digital bus. The data is thus buffered and driven back onto the digital bus during the active |
| 5490155 |
Error correction system for n bits using error correcting code designed for fewer than n bits |
February 6, 1996 |
| A computer system includes an error detection and correction system for detecting and correcting single-bit errors, two-adjacent-bit errors, and four-adjacent-bit errors. Two identical error detection and correction (EDC) circuits are connected to the system memory array, and each EDC |
| 5157277 |
Clock buffer with adjustable delay and fixed duty cycle output |
October 20, 1992 |
| A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching |
| 5050170 |
Apparatus for combining signals from first and second information processing elements |
September 17, 1991 |
| A formatter for combining timing signals with data from an algorithmic pattern generator (APG). In the disclosed embodiment, the formatter receives address signals from an APG and timing signals from a timing unit. Each timing signal from the timing unit corresponds to an address sig |
| 4984213 |
Memory block address determination circuit |
January 8, 1991 |
| An adder and a comparator form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The |
| 4864160 |
Timing signal generator |
September 5, 1989 |
| A timing generator for generating timing signals representing the leading and trailing edges of test pulses. In one embodiment of the invention, a period circuit repetitively measures time intervals, or periods, based on signals from a clock circuit, and a marker circuit generates timing |
