| Patent Number |
Title Of Patent |
Date Issued |
| 7089439 |
Architecture and method for output clock generation on a high speed memory device |
August 8, 2006 |
| An output clock for a memory device having a read latency more than one clock cycle includes a clock generator at a central location on the device. A clock channel couples the clock generator to output structures. A timing path emulates the address/data paths in the memory, and is re |
| 6975260 |
Geometric D/A converter for a delay-locked loop |
December 13, 2005 |
| A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of k.sup.n. The geomet |
| 6947349 |
Apparatus and method for producing an output clock pulse and output clock generator using same |
September 20, 2005 |
| A method and apparatus generates output clock pulses, having leading and trailing edges that are adjusted in a pulse forming processor, according to the relative phase of an output clock and output data. Dynamic adjustment of the leading and trailing edges of output clock pulses impr |
| 6941417 |
High-speed low-power CAM-based search engine |
September 6, 2005 |
| The disclosed invention presents a method and apparatus to a one dimensional prefix search problem. The problem consists looking up the best match to a word out of a table of one-dimensional prefixes. The invention addresses the problems with prior art of high power consumption, larg |
| 6891774 |
Delay line and output clock generator using same |
May 10, 2005 |
| A delay line for an adjustable, high speed clock generator is based on two-stage multiplexing, in which for all pairs of adjacent taps, a change from a current tap to an adjacent tap in the pair is executed by switching only one of the first stage and second stage multiplexers. Control s |
| 6819278 |
Geometric D/A converter for a delay-locked loop |
November 16, 2004 |
| A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of k.sup.n. The geomet |
| 6734815 |
Geometric D/A converter for a delay-locked loop |
May 11, 2004 |
| A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of k.sup.n. The geomet |
