| Patent Number |
Title Of Patent |
Date Issued |
| 7231570 |
Method and apparatus for multi-level scan compression |
June 12, 2007 |
| A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or mor |
| 7210082 |
Method for performing ATPG and fault simulation in a scan-based integrated circuit |
April 24, 2007 |
| A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compiling 704 the RTL |
| 7124342 |
Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based in |
October 17, 2006 |
| A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, e |
| 7058869 |
Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circui |
June 6, 2006 |
| A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT |
| 7032148 |
Mask network design for scan-based integrated circuits |
April 18, 2006 |
| A method and apparatus for selectively masking off unknown (`x`) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or |
