| Patent Number |
Title Of Patent |
Date Issued |
| 6903586 |
Gain control circuitry for delay locked loop circuit |
June 7, 2005 |
| A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current |
| 6859108 |
Current biased phase locked loop |
February 22, 2005 |
| A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector |
| 6831492 |
Common-bias and differential structure based DLL |
December 14, 2004 |
| A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit, including a phase detector for detecting a phase shift between the input reference signal and the |
| 6411142 |
Common bias and differential structure based DLL with fast lockup circuit and current range cali |
June 25, 2002 |
| A delay lock loop (DLL) circuit for generating a precisely delayed output signal relative to an input signal. The DLL circuit includes a phase detector for detecting a phase difference between the input signal and the DLL output signal, a lock circuit for detecting when the difference |
