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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
de Fresart; Edouard D.
Address:
Tempe, AZ
No. of patents:
22
Patents:












Patent Number Title Of Patent Date Issued
8143126 Method for forming a vertical MOS transistor March 27, 2012
A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is
8030153 High voltage TMOS semiconductor device with low gate charge structure and method of making October 4, 2011
A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is b
7919388 Methods for fabricating semiconductor devices having reduced gate-drain capacitance April 5, 2011
Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging reg
7893491 Semiconductor superjunction structure February 22, 2011
Embodiments of semiconductor structures are provided for a semiconductor device employing a superjunction structure. The device includes interleaved regions of first and second semiconductor materials of, respectively, first and second conductivity types and first and second mobiliti
7838389 Enclosed void cavity for low dielectric constant insulator November 23, 2010
Field effect devices and ICs (80, 82, 84) with very low gate-drain capacitance Cgd are provided by forming a substantially empty void (70, 100) between the gate (60') and the drain (27) regions. For vertical FETS a cavity (70, 100) is etched in the semiconductor (SC) (40) and provided
7833858 Superjunction trench device formation methods November 16, 2010
Methods for forming semiconductor structures are provided for a semiconductor device employing a superjunction structure and overlying trench with embedded control gate. An embodiment comprises forming interleaved first and second spaced-apart regions of first and second semiconducto
7651918 Strained semiconductor power device and method January 26, 2010
Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a firs
7602014 Superjunction power MOSFET October 13, 2009
An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length L.sub.acc and a net active dopant concentration of about N.sub.first, a pair of spaced-apart body regions of a second opposite
7598517 Superjunction trench device and method October 6, 2009
Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second
7592230 Trench power device and method September 22, 2009
Means and methods are provided for trench TMOS devices (41-10, 11, 12), comprising, providing a first semiconductor (53, 53') of a first composition having an upper surface (541), with a body portion (54) proximate the upper surface (541), a drift portion (46, 83) spaced apart from t
7510938 Semiconductor superjunction structure March 31, 2009
Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first condu
7378317 Superjunction power MOSFET May 27, 2008
Methods and apparatus are provided for TMOS devices, comprising multiple N-type source regions, electrically in parallel, located in multiple P-body regions separated by N-type JFET regions at a first surface. The gate overlies the body channel regions and the JFET region lying between
7301187 High voltage field effect device and method November 27, 2007
Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92') serially located between
7211477 High voltage field effect device and method May 1, 2007
Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92') serially located between
7074681 Semiconductor component and method of manufacturing July 11, 2006
A semiconductor component includes a substrate (110) having a surface, a channel region (120, 220) located in the substrate, a non-electrically conductive region (130) substantially located below a substantially planar plane defined by the surface of the substrate, a drift region (14
6787858 Carrier injection protection structure September 7, 2004
A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the
6084268 Power MOSFET device having low on-resistance and method July 4, 2000
A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41)
5631484 Method of manufacturing a semiconductor device and termination structure May 20, 1997
A method for forming a semiconductor device includes forming insulated gate regions (122,222) on a substrate (26) using a first photo-masking step, forming a base region (47) through an opening (143) between the insulated gate regions (122,222), and forming a source region (152) within t
5436180 Method for reducing base resistance in epitaxial-based bipolar transistor July 25, 1995
One preferred method for making a semiconductor structure includes altering the direction, and optionally the position, of a polycrystalline grain boundary (38) in a base layer (17,21) of an epitaxial base bipolar transistor (10). Altering the grain boundary (38) may be accomplished by
5286661 Method of forming a bipolar transistor having an emitter overhang February 15, 1994
A bipolar transistor (10) is formed by using low temperature epitaxial deposition in order to form a base layer (14) of the transistor (10). A dielectric (16, 17, 18) is applied to the base layer (14) and an emitter opening (21) having sloping sidewalls is formed in the dielectric (16, 1
5273930 Method of forming a non-selective silicon-germanium epitaxial film December 28, 1993
A method of forming a silicon-germanium epitaxial layer using dichlorosilane as a silicon source gas. A semiconductor seed layer (15) is formed on a portion of a semiconductor layer (12) and on a portion of a layer of dielectric material (13). The semiconductor seed layer (15) provid
5272096 Method for making a bipolar transistor having a silicon carbide layer December 21, 1993
A layer of silicon carbide (33, 38, 41) is utilized in forming a bipolar transistor (30, 40). The transistor (30, 40) is formed on a substrate (31, 32) that has a single crystal silicon surface. The layer of silicon carbide (33, 38, 41) is epitaxially formed on the single crystal silicon










 
 
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