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Inventor: Zhuang; Jingcheng
Address: Dallas, TX
No. of patents: 3
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 8014480 |
Zero-delay serial communications circuitry for serial interconnects |
September 6, 2011 |
| Circuitry and methods for supporting serial communications over serial interconnects between circuit modules are provided. A data recovery circuit receives incoming serial data from the serial interconnect path with zero delay. The data recovery circuit includes a data sampler that s |
| 7843275 |
Frequency synthesizer circuitry employing delay line |
November 30, 2010 |
| Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a voltage, which is |
| 7633322 |
Digital loop circuit for programmable logic device |
December 15, 2009 |
| A digital loop circuit--i.e., a phase-locked loop ("PLL") or delay-locked loop ("DLL")--having a simplified digital loop filter, is particularly well-suited for a programmable logic device ("PLD"). The loop filter may be a memory (e.g., a shift register) which counts the early/late or |
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