| Patent Number |
Title Of Patent |
Date Issued |
| 7619276 |
FinFET flash memory device with an extended floating back gate |
November 17, 2009 |
| A floating gate is formed on one side of the semiconductor fin on a floating gate dielectric. A control gate dielectric is formed on the opposite side of the semiconductor fin and on the floating gate. A gate conductor is formed on the control gate dielectric across the semiconductor |
| 7615831 |
Structure and method for fabricating self-aligned metal contacts |
November 10, 2009 |
| A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy |
| 7612270 |
Nanoelectromechanical digital inverter |
November 3, 2009 |
| A digital inverter formed by three carbon nanotubes (CNTs) extending vertically from a substrate, one CNT functioning as first source (S1) and having a first logic signal applied to it, another CNT functioning as second source (S2) and having a second logic signal applied to it, a th |
| 7602021 |
Method and structure for strained FinFET devices |
October 13, 2009 |
| A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device. |
| 7595233 |
Gate stress engineering for MOSFET |
September 29, 2009 |
| Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon |
| 7569892 |
Method and structure for forming self-aligned, dual stress liner for CMOS devices |
August 4, 2009 |
| A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress |
| 7569447 |
Method of forming transistor structure having stressed regions of opposite types |
August 4, 2009 |
| A method of fabrication is provided in which a field effect transistor (FET) is formed having a channel region and source and drain regions adjacent to the channel region. A first stressed region underlies the channel region, in which the first type of stress is either compressive ty |
| 7566609 |
Method of manufacturing a semiconductor structure |
July 28, 2009 |
| There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes |
| 7564081 |
finFET structure with multiply stressed gate electrode |
July 21, 2009 |
| A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and a second stress wh |
| 7560758 |
MOSFETs comprising source/drain recesses with slanted sidewall surfaces, and methods for fabrica |
July 14, 2009 |
| The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. |
| 7560328 |
Strained Si on multiple materials for bulk or SOI substrates |
July 14, 2009 |
| The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substr |
| 7553709 |
MOSFET with body contacts |
June 30, 2009 |
| A semiconductor structure includes a metal oxide semiconductor field effect transistor that includes a body contact region that extends from body region located beneath a channel region that separates a pair of source/drain regions within the metal oxide semiconductor field effect tr |
| 7550354 |
Nanoelectromechanical transistors and methods of forming same |
June 23, 2009 |
| Nanoelectromechanical transistors (NEMTs) and methods of forming the same are disclosed. In one embodiment, an NEMT may include a substrate including a gate, a source region and a drain region; an electromechanically deflectable nanotube member; and a channel member electrically insu |
| 7544994 |
Semiconductor structure with multiple fins having different channel region heights and method of |
June 9, 2009 |
| Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the |
| 7541629 |
Embedded insulating band for controlling short-channel effect and leakage reduction for DSB proc |
June 2, 2009 |
| A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying semiconductor substrate, a dielectric layer may be deposited and etched back to form em |
| 7528451 |
CMOS gate conductor having cross-diffusion barrier |
May 5, 2009 |
| A gate conductor is provided for a transistor pair including an n-type field effect transistor ("NFET") having an NFET active semiconductor region and a p-type field effect transistor ("PFET") having a PFET active semiconductor region, where the NFET and PFET active semiconductor reg |
| 7528027 |
Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channe |
May 5, 2009 |
| An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the |
| 7521307 |
CMOS structures and methods using self-aligned dual stressed layers |
April 21, 2009 |
| A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing |
| 7504696 |
CMOS with dual metal gate |
March 17, 2009 |
| Embodiments herein present a structure and method to make a CMOS with dual metal gates. Specifically, the CMOS comprises a first gate comprising a first metal and a second gate comprising a second metal. The first gate comprises a portion of a first transistor that is complementary to a |
| 7504693 |
Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineeri |
March 17, 2009 |
| Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of e |
| 7504309 |
Pre-silicide spacer removal |
March 17, 2009 |
| A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not |
| 7498602 |
Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets |
March 3, 2009 |
| Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area. |
| 7485524 |
MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating |
February 3, 2009 |
| The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are ep |
| 7485521 |
Self-aligned dual stressed layers for NFET and PFET |
February 3, 2009 |
| Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such |
| 7485520 |
Method of manufacturing a body-contacted finfet |
February 3, 2009 |
| A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the s |
| 7485510 |
Field effect device including inverted V shaped channel region and method for fabrication thereo |
February 3, 2009 |
| A semiconductor structure includes a semiconductor layer that includes an inverted V shaped channel region that allows avoidance of a raised source/drain region within the semiconductor structure. In one embodiment, a generally conventional gate electrode is located over a planar sur |
| 7482656 |
Method and structure to form self-aligned selective-SOI |
January 27, 2009 |
| Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate |
| 7482615 |
High performance MOSFET comprising stressed phase change material |
January 27, 2009 |
| The present invention relates to semiconductor devices that each comprises at least one field effect transistor (FET) containing an intrinsically stressed phase change material layer. The intrinsically stressed phase change material layer is arranged and constructed for creating stress i |
| 7476580 |
Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon a |
January 13, 2009 |
| Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of e |
| 7476579 |
Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film |
January 13, 2009 |
| A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFE |
| 7462915 |
Method and apparatus for increase strain effect in a transistor channel |
December 9, 2008 |
| A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be |
| 7456636 |
Test structures and method of defect detection using voltage contrast inspection |
November 25, 2008 |
| Test structures and a method for voltage contrast (VC) inspection are disclosed. In one embodiment, the test structure includes: a gate stack that is grounded by a ground to maintain the gate stack in an off state during VC inspection, which allows NFET defect detection using VC insp |
| 7452761 |
Hybrid SOI-bulk semiconductor transistors |
November 18, 2008 |
| Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less ex |
| 7446004 |
Method for reducing overlap capacitance in field effect transistors |
November 4, 2008 |
| A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate c |
| 7442619 |
Method of forming substantially L-shaped silicide contact for a semiconductor device |
October 28, 2008 |
| A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, t |
| 7442585 |
MOSFET with laterally graded channel region and method for manufacturing same |
October 28, 2008 |
| The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along |
| 7439110 |
Strained HOT (hybrid orientation technology) MOSFETs |
October 21, 2008 |
| A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a |
| 7436006 |
Hybrid strained orientated substrates and devices |
October 14, 2008 |
| A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material |
| 7423303 |
Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and differe |
September 9, 2008 |
| The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; |
| 7416986 |
Test structure and method for detecting via contact shorting in shallow trench isolation regions |
August 26, 2008 |
| A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed ac |
| 7413961 |
Method of fabricating a transistor structure |
August 19, 2008 |
| The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of fo |
| 7410852 |
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect tran |
August 12, 2008 |
| An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region ad |
| 7397081 |
Sidewall semiconductor transistors |
July 8, 2008 |
| A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconducto |
| 7393751 |
Semiconductor structure including laminated isolation region |
July 1, 2008 |
| A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U |
| 7388257 |
Multi-gate device with high k dielectric for channel top surface |
June 17, 2008 |
| A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The |
| 7385258 |
Transistors having v-shape source/drain metal contacts |
June 10, 2008 |
| A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconduc |
| 7381609 |
Method and structure for controlling stress in a transistor channel |
June 3, 2008 |
| A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow- |
| 7355245 |
Structure for reducing overlap capacitance in field effect transistors |
April 8, 2008 |
| A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate c |
| 7354806 |
Semiconductor device structure with active regions having different surface directions and metho |
April 8, 2008 |
| Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and |
| 7348641 |
Structure and method of making double-gated self-aligned finFET having gates of different length |
March 25, 2008 |
| A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the |
