The present invention relates to a flash memory array. The flash memory array includes at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge
Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the "hot switching" phenomenon from occurri
Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. De
