| Patent Number |
Title Of Patent |
Date Issued |
| 7534732 |
Semiconductor devices with copper interconnects and composite silicon nitride capping layers |
May 19, 2009 |
| Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having |
| 7521304 |
Method for forming integrated circuit |
April 21, 2009 |
| A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes remo |
| 7494885 |
Disposable spacer process for field effect transistor fabrication |
February 24, 2009 |
| According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be fo |
| 7378310 |
Method for manufacturing a memory device having a nanocrystal charge storage region |
May 27, 2008 |
| A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectr |
| 7309650 |
Memory device having a nanocrystal charge storage region and method |
December 18, 2007 |
| A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a secon |
| 7256499 |
Ultra low dielectric constant integrated circuit system |
August 14, 2007 |
| An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in |
| 7208418 |
Sealing sidewall pores in low-k dielectrics |
April 24, 2007 |
| Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k |
| 7183198 |
Method for forming a hardmask employing multiple independently formed layers of a capping materi |
February 27, 2007 |
| A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes th |
| 7169706 |
Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper depositio |
January 30, 2007 |
| An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor |
| 7157335 |
Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact r |
January 2, 2007 |
| The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of |
| 7038320 |
Single damascene integration scheme for preventing copper contamination of dielectric layer |
May 2, 2006 |
| A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer |
| 7033960 |
Multi-chamber deposition of silicon oxynitride film for patterning |
April 25, 2006 |
| Pinholes in a silicon oxynitride film are reduced by PECVD deposition of a plurality of silicon oxynitride sub-layers in a PECVD apparatus containing multiple chambers. Embodiments include forming a layer of amorphous carbon over a conductive layer, such as doped polycrystalline sili |
| 7001840 |
Interconnect with multiple layers of conductive material with grain boundary between the layers |
February 21, 2006 |
| An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of t |
| 6992004 |
Implanted barrier layer to improve line reliability and method of forming same |
January 31, 2006 |
| A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided |
| 6939793 |
Dual damascene integration scheme for preventing copper contamination of dielectric layer |
September 6, 2005 |
| A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, |
| 6900002 |
Antireflective bi-layer hardmask including a densified amorphous carbon layer |
May 31, 2005 |
| An amorphous carbon layer of an antireflective bi-layer hardmask is processed to increase its density prior to patterning of an underlying polysilicon layer using the bi-layer hardmask. The increased density of the layer increases its resistance to polysilicon etch chemistry, thus re |
| 6893967 |
L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials |
May 17, 2005 |
| A multilayer L-shaped spacer is formed of a lower portion comprising a CVD organic material or amorphous carbon, and an upper portion comprised of a protective material. The upper portion is patterned using a photoresist mask. During that patterning, the underlying substrate is protected |
| 6875664 |
Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and AR |
April 5, 2005 |
| A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region |
| 6864556 |
CVD organic polymer film for advanced gate patterning |
March 8, 2005 |
| A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a patt |
| 6803313 |
Method for forming a hardmask employing multiple independently formed layers of a pecvd material |
October 12, 2004 |
| A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that a |
| 6784095 |
Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing |
August 31, 2004 |
| Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to |
| 6773998 |
Modified film stack and patterning strategy for stress compensation and prevention of pattern di |
August 10, 2004 |
| A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The |
| 6764949 |
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabric |
July 20, 2004 |
| A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The |
| 6764947 |
Method for reducing gate line deformation and reducing gate line widths in semiconductor devices |
July 20, 2004 |
| A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask |
| 6756672 |
Use of sic for preventing copper contamination of low-k dielectric layers |
June 29, 2004 |
| A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer |
| 6756300 |
Method for forming dual damascene interconnect structure |
June 29, 2004 |
| For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material dispo |
| 6750127 |
Method for fabricating a semiconductor device using amorphous carbon having improved etch resist |
June 15, 2004 |
| An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides |
| 6724087 |
Laminated conductive lines and methods of forming the same |
April 20, 2004 |
| A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at lea |
| 6713874 |
Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-la |
March 30, 2004 |
| Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ |
| 6699792 |
Polymer spacers for creating small geometry space and method of manufacture thereof |
March 2, 2004 |
| In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature confor |
| 6689684 |
Cu damascene interconnections using barrier/capping layer |
February 10, 2004 |
| Interconnects to an underlying Cu feature are formed with improved reliability by replacing a portion of the capping layer in the bottom of an opening in an overlying dielectric layer, e.g., an ILD, with a barrier material, such as Ta or TaN. During Ar sputter etching to round the ILD |
| 6677679 |
Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers |
January 13, 2004 |
| A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier |
| 6663787 |
Use of ta/tan for preventing copper contamination of low-k dielectric layers |
December 16, 2003 |
| A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier |
| 6653735 |
CVD silicon carbide layer as a BARC and hard mask for gate patterning |
November 25, 2003 |
| A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pa |
| 6632707 |
Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning |
October 14, 2003 |
| A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the |
| 6627973 |
Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device |
September 30, 2003 |
| A method of eliminating voids in the interlayer dielectric material of 0.18-.mu.m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-.mu.m flash memor |
| 6586842 |
Dual damascene integration scheme for preventing copper contamination of dielectric layer |
July 1, 2003 |
| A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, |
| 6577009 |
Use of sic for preventing copper contamination of dielectric layer |
June 10, 2003 |
| A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer |
| 6576982 |
Use of sion for preventing copper contamination of dielectric layer |
June 10, 2003 |
| A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer |
| 6576545 |
Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-l |
June 10, 2003 |
| Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-sit |
| 6566283 |
Silane treatment of low dielectric constant materials in semiconductor device manufacturing |
May 20, 2003 |
| Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to |
| 6518646 |
Semiconductor device with variable composition low-k inter-layer dielectric and method of making |
February 11, 2003 |
| Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectr |
| 6518167 |
Method of forming a metal or metal nitride interface layer between silicon nitride and copper |
February 11, 2003 |
| A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic |
| 6489253 |
Method of forming a void-free interlayer dielectric (ILD0) for 0.18-.mu.m flash memory technolog |
December 3, 2002 |
| A method of eliminating voids in the interlayer dielectric material of 0.18-.mu.m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-.mu.m flash memor |
| 6465361 |
Method for preventing damage of low-k dielectrics during patterning |
October 15, 2002 |
| A process for manufacturing a semiconductor device includes forming a first metallization level, forming a first etch stop layer, forming a low-k dielectric layer, forming a cap layer, depositing a resist, forming an opening; removing the resist, curing the dielectric material, etching t |
