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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Yoshioka; Ken
Address:
Kudamatsu, JP
No. of patents:
5
Patents:












Patent Number Title Of Patent Date Issued
6309980 Semiconductor integrated circuit arrangement fabrication method October 30, 2001
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
6245202 Plasma treatment device June 12, 2001
In a high-frequency inductive plasma etching apparatus, a space between an antenna to which a high-frequency power is fed and a processing chamber is insulated with an insulating material having a suitable thickness, while the antenna is protected from a plasma or a reactive gas for plas
6074958 Semiconductor integrated circuit arrangement fabrication method June 13, 2000
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
5962347 Semiconductor integrated circuit arrangement fabrication method October 5, 1999
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
5874013 Semiconductor integrated circuit arrangement fabrication method February 23, 1999
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta










 
 
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