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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Yeh; Jack
Address:
Hsin-Chu, TW
No. of patents:
15
Patents:












Patent Number Title Of Patent Date Issued
7417278 Method to increase coupling ratio of source to floating gate in split-gate flash August 26, 2008
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
7001809 Method to increase coupling ratio of source to floating gate in split-gate flash February 21, 2006
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6635922 Method to fabricate poly tip in split gate flash October 21, 2003
A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the mini
6544828 Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM April 8, 2003
A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is
6465841 Split gate flash memory device having nitride spacer to prevent inter-poly oxide damage October 15, 2002
A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers s
6465836 Vertical split gate field effect transistor (FET) device October 15, 2002
Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field e
6403494 Method of forming a floating gate self-aligned to STI on EEPROM June 11, 2002
A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory
6380583 Method to increase coupling ratio of source to floating gate in split-gate flash April 30, 2002
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6333228 Method to improve the control of bird's beak profile of poly in split gate flash December 25, 2001
A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing pro
6297099 Method to free control tunneling oxide thickness on poly tip of flash October 2, 2001
A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is
6228695 Method to fabricate split-gate with self-aligned source and self-aligned floating gate to contro May 8, 2001
A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate
6174772 Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate January 16, 2001
A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers s
6165845 Method to fabricate poly tip in split-gate flash December 26, 2000
A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the mini
6159801 Method to increase coupling ratio of source to floating gate in split-gate flash December 12, 2000
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6127229 Process of forming an EEPROM device having a split gate October 3, 2000
There is presented an improved method of fabricating an EEPROM device with a split gate. In the method, a silicon substrate is provided having spaced and parallel recessed oxide regions that isolate component regions where the oxide regions project above the top surface of the substrate.










 
 
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