| Patent Number |
Title Of Patent |
Date Issued |
| 5121013 |
Noise reducing output buffer circuit with feedback path |
June 9, 1992 |
| Electrical buffer output circuitry includes a first high branch having a high signal input terminal, a low input branch having a low input signal input terminal, and a signal output for the buffer circuitry. Either the high branch or the low branch is turned on in response to a signal at |
| 4928260 |
Content addressable memory array with priority encoder |
May 22, 1990 |
| A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a p |
| 4890260 |
Content addressable memory array with maskable and resettable bits |
December 26, 1989 |
| A content addressable memory array includes an array of M words containing bits configured in N bits for each word. One of the bits in each of the words is a settable skip bit, and during a search of the memory array, the array is examined to detect the presence therein of skip bits. If |
| 4888731 |
Content addressable memory array system with multiplexed status and command information |
December 19, 1989 |
| A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the |
| 4716552 |
Method and apparatus for non-destructive access of volatile and non-volatile data in a shadow me |
December 29, 1987 |
| Circuitry, including a non-volatile dynamic random access memory cell, a sense amplifier and a data latch affords non-destructive accessing and comparison of the data stored within the volatile and non-volatile portion of the memory cell. In certain applications, it is desirable to resto |
| 4672580 |
Memory cell providing simultaneous non-destructive access to volatile and non-volatile data |
June 9, 1987 |
| A memory cell providing separate storage of volatile and non-volatile data. The volatile and non-volatile data elements, which are not necessarily duplicative, can be non-destructively accessed within a single memory clock cycle via separate volatile and non-volatile bit lines. The cell |
