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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Yang; Fu-Liang
Address:
Tainan, TW
No. of patents:
29
Patents:












Patent Number Title Of Patent Date Issued
6278189 High density integrated circuits using tapered and self-aligned contacts August 21, 2001
A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with red
6277709 Method of forming shallow trench isolation structure August 21, 2001
A method for manufacturing a shallow trench isolation structure. A pad oxide layer and a mask layer are formed over a substrate. Portions of the mask layer, the pad layer and substrate are removed forming a trench. Oxidation of the substrate within the trench forms a linear oxide layer.
6261923 Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local in July 17, 2001
A method for forming planarized isolation using a nitride hard mask and two CMP steps is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride and pad oxide layers are etched through where they are not covered
6248643 Method of fabricating a self-aligned contact June 19, 2001
A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, f
6239034 Method of manufacturing inter-metal dielectric layers for semiconductor devices May 29, 2001
A method of manufacturing an inter-metal level dielectric layer for a semiconductor device. The method includes forming spaced conductive lines. Next, a first conformal silicon oxide film (barrier layer) is formed over the spaced conductive lines. Gaps or valleys are between the metal li
6180489 Formation of finely controlled shallow trench isolation for ULSI process January 30, 2001
A method for forming planarized shallow trench isolation is described. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the nitride layer into the semiconductor substrate wherein there are at least one wide
6174815 Method for planarizing DRAM cells January 16, 2001
A method for planarizing DRAM cells comprising the steps of providing a silicon substrate having a field oxide layer, an oxide layer and a capacitor formed thereon, then forming a first dielectric layer over the substrate. Next, portions of the first dielectric layer is etched back to
6171929 Shallow trench isolator via non-critical chemical mechanical polishing January 9, 2001
A method for implementing shallow trench isolation by using a non-critical chemical mechanical polishing method in an integrated circuit. After STI regions are etched and insulator oxide layer is deposited and etched back, a planarized insulator oxide layer is formed. The corners of sili
6159822 Self-planarized shallow trench isolation December 12, 2000
A method for implementing self-planarized shallow trench isolation in an integrated circuit. A planarized insulator oxide layer is formed after shallow trench isolation is etched and insulator oxide layer is deposited and etched back. The corners of silicon nitride layer over active area
6159821 Methods for shallow trench isolation December 12, 2000
A method for forming self-rounded shallow trench isolation is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is then deposited overlying the pad oxide layer. Isolation trenches are then etched through the nitride and pad oxide laye
6140240 Method for eliminating CMP induced microscratches October 31, 2000
A method of removing microscratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structures includes a semiconductor substrate having at least one dielectric layer formed thereon followed by a chemical mechanical polishing process for pl
6130127 Method for making dynamic random access memory cells having cactus-shaped stacked capacitors wit October 10, 2000
An array of DRAM cells having cactus-shaped stacked capacitors with increased capacitance is achieved. A first planar insulating layer is formed, and a silicon nitride (Si.sub.3 N.sub.4) layer having openings over the FET source/drain areas for node contacts is formed. A thick third
6071789 Method for simultaneously fabricating a DRAM capacitor and metal interconnections June 6, 2000
A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate. The method comprises the steps of: forming a first dielectric layer over said cell array area and said periphery; forming a plurality of first conta
6060348 Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technolog May 9, 2000
A method for forming planarized isolation by combining LOCOS and STI isolation processes is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride layer and pad oxide layer are etched through where they are not
6057210 Method of making a shallow trench isolation for ULSI formation via in-direct CMP process May 2, 2000
A silicon dioxide layer and a silicon nitride layer are formed on the wafer. Subsequently, a plurality of shallow trenches are generated in the wafer. A HDP-CVD oxide having protruding portions is refilled into the trenches and formed on the silicon nitride layer for isolation. A wet etc
6054017 Chemical mechanical polishing pad with controlled polish rate April 25, 2000
A chemical mechanical polish apparatus (FIG. 3B) for planarizing a semiconductor wafer (31) is disclosed. The apparatus includes a polishing pad (21) and a polishing head (32). The polishing pad includes a surface for polishing the semiconductor wafer. The surface has a hole (20). The
6037259 Method for forming identifying characters on a silicon wafer March 14, 2000
After identifying characters are written on the wafer surface 16 as a pattern of small holes 19 formed with a laser in the wafer I.D. stage of a semiconductor manufacturing process, the wafer surface in the region of the I.D. is polished to break loose deposits of silicon 20 that are lef
6037216 Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and periphe March 14, 2000
A process for simultaneously forming storage node structures, for a DRAM cell, and an interconnect structure, for a peripheral region of a DRAM chip, has been developed. The process features the use of dual damascene procedures, with the first damascene procedure used to create the stora
5994228 Method of fabricating contact holes in high density integrated circuits using taper contact and November 30, 1999
A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with red
5956594 Method for simultaneously forming capacitor plate and metal contact structures for a high densit September 21, 1999
A method for creating a DRAM device, featuring the simultaneous formation of a capacitor plate, used for a stacked capacitor structure, and the formation of a metal contact structure, and of a word line contact structure, has been developed. The process features the deposition of a b
5888124 Apparatus for polishing and cleaning a wafer March 30, 1999
An apparatus for polishing and cleaning a semiconductor wafer (3028) is disclosed to substantially improve the efficiency of chemical-mechanical polishing. The apparatus reduces contamination to a clean room during fabrication of VLSI circuits. The apparatus includes a table (3026) s
5854130 Method of forming multilevel interconnects in semiconductor devices December 29, 1998
A method for forming multilevel interconnects in a semiconductor IC device is provided. The method involves a simplified planarization process for planarization of inter-metal dielectrics that allows for easy and cost-effective fabrication of the device. By this method, an insulating
5851874 Method of planarizing memory cells December 22, 1998
A planarzation process is crucial for submicron VLSI or ULSI fabrication, The method of the present invention comprises forming a stacked capacitor contact on a substrate, forming a first dielectric layer on the capacitor contact. Next an etching process is performed to etchback the firs
5834359 Method of forming an isolation region in a semiconductor substrate November 10, 1998
A method for forming an isolation region in a semiconductor substrate is disclosed. The present invention includes forming an insulating layer on the semiconductor substrate, and then forming a dielectric layer on the insulating layer. After patterning to etch portions of the dielectric
5804852 Stacked capacitor DRAM structure featuring a multiple crown shaped polysilicon lower electrode September 8, 1998
A multiple crown shaped polysilicon structure, used for a lower electrode of a DRAM stacked capacitor structure, has been developed. The multiple crown shaped, lower electrode, is formed overlying, and contacting a polysilicon fill layer, that is located between insulator encapsulated
5804489 Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etch September 8, 1998
The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using
5792689 Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random August 11, 1998
A method is described using a single photoresist mask to make a double-crown-shaped DRAM capacitor self-aligned to the capacitor node contact. After forming the DRAM FETs and the bit lines, a planar BPSG layer, a first polysilicon layer, and a CVD oxide layer are deposited. A node co
5677227 Method of fabricating single crown, extendible to triple crown, stacked capacitor structures, us October 14, 1997
A process for creating a stacked capacitor, dynamic random access memory device, featuring increased capacitor surface area, resulting from a polysilicon, triple crown shaped, lower electrode structure, and also featuring self-alignment of the stacked capacitor contact structure, to a
5656556 Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures August 12, 1997
An improved method for forming a planar borophosphosilicate glass (BPSG) insulating layer having a reduced thermal budget was achieved. The method involves forming a multilayer BPSG comprised of four layers with different boron and phosphorus concentrations in each layer. The first layer










 
 
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