| Patent Number |
Title Of Patent |
Date Issued |
| 6430670 |
Apparatus and method for a virtual hashed page table |
August 6, 2002 |
| The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of |
| 6408373 |
Method and apparatus for pre-validating regions in a virtual addressing scheme |
June 18, 2002 |
| A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can |
| 6393544 |
Method and apparatus for calculating a page table index from a virtual address |
May 21, 2002 |
| A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A "short format" page table is provided for each virtual region, is linear, has a linear entry for each translation in |
| 6230248 |
Method and apparatus for pre-validating regions in a virtual addressing scheme |
May 8, 2001 |
| A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can |
| 6216214 |
Apparatus and method for a virtual hashed page table |
April 10, 2001 |
| The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of |
| 6209085 |
Method and apparatus for performing process switching in multiprocessor computer systems |
March 27, 2001 |
| A method and apparatus for reducing the amount of data copied during process switches. A method for reducing the amount of data copied during process switches is provided. In response to a processor performing a process switch to a process, a first write indication corresponding to the |
| 6012132 |
Method and apparatus for implementing a page table walker that uses a sliding field in the virtu |
January 4, 2000 |
| A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a |
| 5940872 |
Software and hardware-managed translation lookaside buffer |
August 17, 1999 |
| A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-managed. The TLB also includes a se |
| 5918251 |
Method and apparatus for preloading different default address translation attributes |
June 29, 1999 |
| A method and apparatus for streamlining the installation of virtual to physical address translations into a translation unit. According to one aspect of the invention, an apparatus for use in a computer system is provided that generally includes a translation unit, a default attribute |
| 5809563 |
Method and apparatus utilizing a region based page table walk bit |
September 15, 1998 |
| A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookaside buffer (TLB) is configured to provide page table entries to build a physical address. The TLB is supplemented |
