| Patent Number |
Title Of Patent |
Date Issued |
| 7203116 |
Semiconductor memory device |
April 10, 2007 |
| With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions f |
| 7082063 |
Semiconductor memory device |
July 25, 2006 |
| With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions f |
| 6928017 |
Semiconductor memory device |
August 9, 2005 |
| With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a |
| 6851017 |
Semiconductor memory |
February 1, 2005 |
| The present invention provides a semiconductor memory capable of shortening a refresh cycle time and reducing power consumption at refresh. The semiconductor memory includes an address input circuit for generating each of internal address signals, a redundant judgement circuit for receiv |
| 6625079 |
Semiconductor memory device |
September 23, 2003 |
| With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a |
| 6576946 |
Semiconductor device comprising capacitor cells, bit lines, word lines, and MOS transistors in a |
June 10, 2003 |
| Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized mor |
| 6563759 |
Semiconductor memory device |
May 13, 2003 |
| In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a si |
| 6563755 |
Semiconductor memory device |
May 13, 2003 |
| A semiconductor memory device realizing a reduced cycle time while improving the ease of use is to be provided. Where a memory cell requires a periodic refresh action to hold stored information, a time multiplexing mode of performing, when a first memory operation on any memory cell to |
| 5963483 |
Synchronous memory unit |
October 5, 1999 |
| A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the |
