| Patent Number |
Title Of Patent |
Date Issued |
| 7530056 |
Method and system for detecting runtime defects in a program by comparing correct and incorrect |
May 5, 2009 |
| The invention provides an improved method and method for locating the origin of runtime defect in software programs. A differential debugging technique may be implemented to locate the diversion point where two programs start to behave differently. In one approach, the method general |
| 7480686 |
Method and apparatus for executing packed shift operations |
January 20, 2009 |
| A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift |
| 7461109 |
Method and apparatus for providing packed shift operations in a processor |
December 2, 2008 |
| A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register |
| 7451169 |
Method and apparatus for providing packed shift operations in a processor |
November 11, 2008 |
| A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that |
| 7430733 |
Method for validation of binary code transformations |
September 30, 2008 |
| A method of validating binary code transformation in one aspect includes analyzing original program and transform program. Control flow graphs are generated for both programs. The two graphs are traversed to create respective linear invariant representations. The linear representations |
| 7117232 |
Method and apparatus for providing packed shift operations in a processor |
October 3, 2006 |
| A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that |
| 6901420 |
Method and apparatus for performing packed shift operations |
May 31, 2005 |
| A method and apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted |
| 6738793 |
Processor capable of executing packed shift operations |
May 18, 2004 |
| An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed |
| 6631389 |
Apparatus for performing packed shift operations |
October 7, 2003 |
| An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed |
| 6275834 |
Apparatus for performing packed shift operations |
August 14, 2001 |
| An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed |
| 6119216 |
Microprocessor capable of unpacking packed data in response to a unpack instruction |
September 12, 2000 |
| A microprocessor capable of unpacking packed data in response to an unpack instruction. The microprocessor having a a storage area to store a first packed data and a second packed data respectively including a first plurality of data elements and a second plurality of data elements, |
| 6070237 |
Method for performing population counts on packed data types |
May 30, 2000 |
| A novel processor for manipulating packed data. The packed data includes a first data element D1 and a second data element D2. Each of said data elements has a predetermined number of bits. The processor comprises a decoder, a register, and a circuit. The decoder is for decoding a contro |
| 5881275 |
Method for unpacking a plurality of packed data into a result packed data |
March 9, 1999 |
| A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for |
| 5819101 |
Method for packing a plurality of packed data elements in response to a pack instruction |
October 6, 1998 |
| A method for manipulating packed data in a computer system. The method includes the steps of decoding a Single Instruction Multiple Data (SIMD) pack instruction. The instruction identifies a first and second packed data respectively including a first plurality of data elements and a |
| 5818739 |
Processor for performing shift operations on packed data |
October 6, 1998 |
| A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a fist location. The second source addre |
| 5802336 |
Microprocessor capable of unpacking packed data |
September 1, 1998 |
| A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for |
| 5677862 |
Method for multiplying packed data |
October 14, 1997 |
| A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source addr |
| 5675526 |
Processor performing packed data multiplication |
October 7, 1997 |
| A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source addr |
| 5666298 |
Method for performing shift operations on packed data |
September 9, 1997 |
| A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source addr |
| 5265213 |
Pipeline system for executing predicted branch target instruction in a cycle concurrently with t |
November 23, 1993 |
| A pipeline instruction processor for executing instructions stored in an instruction memory, including a plurality of branch instructions. The instruction processor includes a branch target buffer which contains target instructions and target addresses corresponding to branch instruc |
