| Patent Number |
Title Of Patent |
Date Issued |
| 7588993 |
Alignment for backside illumination sensor |
September 15, 2009 |
| An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate bet |
| 7553689 |
Semiconductor device with micro-lens and method of making the same |
June 30, 2009 |
| A semiconductor device including a semiconductor substrate having a photosensor formed therein; a first layer overlying the substrate, the first layer includes a portion having a generally concave shaped surface being the negative shaped of a micro-lens to be formed there over; a sec |
| 7507596 |
Method of fabricating a high quantum efficiency photodiode |
March 24, 2009 |
| The present invention is CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS image sensor with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless c |
| 7485940 |
Guard ring structure for improving crosstalk of backside illuminated image sensor |
February 3, 2009 |
| The present disclosure provides a backside illuminated semiconductor device. The device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements is designed and configured to receive |
| 7432578 |
CMOS image sensor with enhanced photosensitivity |
October 7, 2008 |
| A photosensitive device is disclosed which comprises a semiconductor substrate, at least one reverse biased device, such as a P-N junction diode formed in the semiconductor substrate, and at least one photosensitive layer disposed above the semiconductor substrate and substantially c |
| 7432576 |
Grid metal design for large density CMOS image sensor |
October 7, 2008 |
| A new grid metal design for image sensors is disclosed which is comprised of a semiconductor image sensor chip having a pixel region covering most of the chip and a logic circuit region on the chip periphery. The pixel region contains, an array of image pixels where for each image pixel |
| 7423306 |
CMOS image sensor devices |
September 9, 2008 |
| A pixel comprises a substrate comprising a first well region formed in a top portion of the substrate, having a first conductivity type. A plurality of shallow trench isolation (STI) structures is formed in the first well region of the substrate, defining a pixel region over the subs |
| 7388187 |
Cross-talk reduction through deep pixel well implant for image sensors |
June 17, 2008 |
| An image sensor device includes a semiconductor substrate having a first type of conductivity, a semiconductor layer having the first type of conductivity formed on the semiconductor substrate, and pixels formed in the semiconductor layer. The semiconductor layer includes a first deep |
| 7338830 |
Hollow dielectric for image sensor |
March 4, 2008 |
| A plurality of apertures is formed in at least one first insulating layer disposed over a sensor formed in a semiconductor substrate. A second insulating layer is disposed over the at least one first insulating layer and the plurality of apertures in the at least one first insulating |
| 7332368 |
Light guide for image sensor |
February 19, 2008 |
| A new method to form an image sensor device is achieved. The method comprises forming an image sensing array in a substrate comprising a plurality of light detecting diodes with spaces between the diodes. A first dielectric layer is formed overlying the diodes but not the spaces. The |
| 7282757 |
MIM capacitor structure and method of manufacture |
October 16, 2007 |
| A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion o |
| 7253458 |
CMOS image sensor |
August 7, 2007 |
| A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 .mu.m. At least one dielectric layer is disposed on the s |
| 7232697 |
Semiconductor device having enhanced photo sensitivity and method for manufacture thereof |
June 19, 2007 |
| Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first |
| 7208369 |
Dual poly layer and method of manufacture |
April 24, 2007 |
| Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some |
| 7067891 |
Sensor element having elevated diode with sidewall passivated bottom electrode |
June 27, 2006 |
| Each of an elevated diode sensor optoelectronic product and a method for fabricating the elevated diode sensor optoelectronic product employs a sidewall passivation dielectric layer passivating a sidewall of a patterned conductor layer which serves as a bottom electrode for an elevat |
| 7061028 |
Image sensor device and method to form image sensor device |
June 13, 2006 |
| A new method to form an image sensor device is achieved. The method comprises forming an image sensing array in a substrate comprising a plurality of light detecting diodes with spaces between the diodes. A first dielectric layer is formed overlying the diodes but not the spaces. The |
| 7038232 |
Quantum efficiency enhancement for CMOS imaging sensor with borderless contact |
May 2, 2006 |
| The present invention is a CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS image sensor with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless |
| 6982443 |
Hollow dielectric for image sensor |
January 3, 2006 |
| A plurality of apertures is formed in at least one first insulating layer disposed over a sensor formed in a semiconductor substrate. A second insulating layer is disposed over the at least one first insulating layer and the plurality of apertures in the at least one first insulating |
| 6815787 |
Grid metal design for large density CMOS image sensor |
November 9, 2004 |
| A new grid metal design for image sensors is disclosed which is comprised of a semiconductor image sensor chip having a pixel region covering most of the chip and a logic circuit region on the chip periphery. The pixel region contains an array of image pixels where for each image pixel t |
| 6710413 |
Salicide field effect transistors with improved borderless contact structures and a method of fa |
March 23, 2004 |
| An improved borderless contact structure for salicide field effect transistors (FETs) has been achieved. Salicide FETs are formed on device areas surrounded by a shallow trench isolation (STI) using a first rapid thermal anneal to form a metal silicide on the source/drain contacts and |
| 6707080 |
Method for making spectrally efficient photodiode structures for CMOS color imagers |
March 16, 2004 |
| A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N d |
| 6642076 |
Asymmetrical reset transistor with double-diffused source for CMOS image sensor |
November 4, 2003 |
| A new method to form CMOS image sensors in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. Sensor diodes are formed in the semiconductor substrate each comprising a first terminal and a second terminal. Gates are form |
| 6531752 |
Stripe photodiode element with high quantum efficiency for an image sensor cell |
March 11, 2003 |
| A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine shaped region results in increase |
| 6518085 |
Method for making spectrally efficient photodiode structures for CMOS color imagers |
February 11, 2003 |
| A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N d |
| 6350662 |
Method to reduce defects in shallow trench isolations by post liner anneal |
February 26, 2002 |
| A method to form shallow trench isolations with reduced substrate defects by using a nitrogen anneal is achieved. A silicon substrate is provided. The silicon substrate is etched where not protected by a photoresist mask to form shallow trenches where shallow trench isolations are planne |
| 6335249 |
Salicide field effect transistors with improved borderless contact structures and a method of fa |
January 1, 2002 |
| A process for making improved borderless contact structure to salicide field effect transistors (FETs) has been achieved. Salicide FETs are formed on device areas surrounded by a shallow trench isolation (STI) using a first rapid thermal anneal (RTA-1) to form a metal silicide on the |
| 6323054 |
Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor |
November 27, 2001 |
| A process for fabricating a lateral photodiode element, for an image sensor cell, with an increased depletion region, has been developed. The process features protecting a portion of the semiconductor substrate from ion implantation procedures used to create the P well, and the N well |
| 6309905 |
Stripe photodiode element with high quantum efficiency for an image sensor cell |
October 30, 2001 |
| A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine shaped region results in increase |
| 6265271 |
Integration of the borderless contact salicide process |
July 24, 2001 |
| A method for integrating salicide and borderless contact processes while avoiding current leakage at the shallow trench isolation edge is described. Shallow trench isolation (STI) regions are formed in a semiconductor substrate electrically isolating an active area from other active |
| 6232194 |
Silicon nitride capped poly resistor with SAC process |
May 15, 2001 |
| A new method of forming a polysilicon resistor having precisely controlled resistance by using a thin silicon nitride cap over the polysilicon resistor is described. A dielectric layer is provided on a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric lay |
| 6222214 |
Plug structure and process for forming stacked contacts and metal contacts on static random acce |
April 24, 2001 |
| A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connection |
| 6194258 |
Method of forming an image sensor cell and a CMOS logic circuit device |
February 27, 2001 |
| A process for integrating the formation of salicided, CMOS logic devices, for a CMOS logic circuit region, and of a non-salicided, photodiode element, for a image sensor cell region, has been developed. The process features the selective formation of a thin silicon oxide layer on the top |
| 6165880 |
Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circ |
December 26, 2000 |
| A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon n |
| 6136633 |
Trench-free buried contact for locos isolation |
October 24, 2000 |
| A new method of forming an improved buried contact junction is described. A gate oxide layer is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited over the gate oxide layer. A photoresist mask is formed over the first polysilicon layer havi |
| 6071798 |
Method for fabricating buried contacts |
June 6, 2000 |
| The present invention provides a novel method for fabricating a buried contact extending under the first conductive layer 16 and subjacent first insulating layer 14. A first insulating layer 14 and a first conductive layer are formed over a silicon substrate 10 having isolation structure |
| 6046103 |
Borderless contact process for a salicide devices |
April 4, 2000 |
| A process for forming a borderless contact opening to an active device region, overlaid with a metal silicide layer, has been developed. The borderless contact opening is formed in a composite insulator layer, comprised with an overlying, thick ILD layer, and a thin, underlying silic |
| 6040227 |
IPO deposited with low pressure O.sub.3 -TEOS for planarization in multi-poly memory technology |
March 21, 2000 |
| The present invention provides a method of inter-poly oxide (IPO) layer underlying a polysilicon resistor in a memory product. The IPO layer 15 is formed by a modified low pressure SACVD-O.sub.3 -TEOS process that gives the IPO layer a smoother surface and good planarization. This IPO la |
| 6001731 |
Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process |
December 14, 1999 |
| A method for providing a chemical mechanical polishing planarization process for preventing multi-polysilicon and multi-metal level electrical shorts, which includes briefly the sequential processing steps of i) providing an insulating layer to a first thickness over a device wafer w |
| 5926697 |
Method of forming a moisture guard ring for integrated circuit applications |
July 20, 1999 |
| An improved and new structure and method for forming a guard ring in an integrated circuit having at least one level of polysilicon wiring has been developed. The guard ring is formed without necessitating additional manufacturing process steps and the guard ring is bonded to the sem |
| 5867087 |
Three dimensional polysilicon resistor for integrated circuits |
February 2, 1999 |
| A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the |
| 5796135 |
Process to fabricate stacked capacitor dram and low power thin film transistor sram devices on a |
August 18, 1998 |
| A fabrication process for integrating stacked capacitor, DRAM devices, and thin film transistor, SRAM devices, has been developed. The fabrication process features combining key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM a |
| 5677557 |
Method for forming buried plug contacts on semiconductor integrated circuits |
October 14, 1997 |
| A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over o |
| 5668380 |
Reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resist |
September 16, 1997 |
| Reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The structure involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening i |
| 5576243 |
Process for forming stacked contacts and metal contacts on static random access memory having th |
November 19, 1996 |
| A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connection |
| 5547892 |
Process for forming stacked contacts and metal contacts on static random access memory having th |
August 20, 1996 |
| A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connection |
| 5545585 |
Method of making a dram circuit with fin-shaped stacked capacitors |
August 13, 1996 |
| A novel method is presented for making an array of stacked capacitors on DRAM circuits. Chemical/Mechanical Polishing (CMP) is used to form "globally" a very planar surface on an insulating layer across the substrate. By virtue of this global planarization three additional insulating |
| 5534451 |
Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structur |
July 9, 1996 |
| A method for fabricating reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The method involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the |
