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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Wu; Tsang Jiuh
Address:
Taichung, TW
No. of patents:
7
Patents:




Patent Number Title Of Patent Date Issued
7265060 Bi-level resist structure and fabrication method for contact holes on semiconductor substrates September 4, 2007
An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique comb
7253112 Dual damascene process August 7, 2007
A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill
6914007 In-situ discharge to avoid arcing during plasma etch processes July 5, 2005
A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt
6797630 Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach September 28, 2004
A method for forming a dual damascene opening comprising the following steps. A structure having an exposed conductive structure formed therein is provided. An etch stop layer is formed over the structure and the exposed conductive structure. A dielectric layer is formed over the etch
6780782 Bi-level resist structure and fabrication method for contact holes on semiconductor substrates August 24, 2004
An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique comb
6720256 Method of dual damascene patterning April 13, 2004
An improved method of patterning photoresist during formation of damascene structures is provided which involves a process that is resistant to poisoning from adjacent layers. An inert resin is used to fill vias in a damascene stack. Then a second stack comprised of an underlayer, a
6551938 N2/H2 chemistry for dry development in top surface imaging technology April 22, 2003
A method of bi-layer top surface imaging, comprising the following steps. A structure having a lower layer formed thereover is provided. An upper silicon-containing photoresist layer is formed upon the lower layer. The upper silicon-containing photoresist layer is selectively exposed to


 
 
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