| Patent Number |
Title Of Patent |
Date Issued |
| 7187046 |
Method of forming an N channel and P channel finfet device on the same semiconductor substrate |
March 6, 2007 |
| A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin |
| 6649308 |
Ultra-short channel NMOSFETS with self-aligned silicide contact |
November 18, 2003 |
| The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are formed in the substrate. A metal |
| 6569729 |
Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application |
May 27, 2003 |
| A method of reducing the aspect ratio for dry etch processes used to form contact hole and storage node openings in composite insulator layers, to expose regions of CMOS devices used for embedded memory cell applications, has been developed. The method features formation of CMOS devices |
| 6555438 |
Method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source |
April 29, 2003 |
| A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrate. A thermal oxide layer is forme |
| 6548362 |
Method of forming MOSFET with buried contact and air-gap gate structure |
April 15, 2003 |
| A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations. Then, a polysilicon layer and a |
| 6432785 |
Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-a |
August 13, 2002 |
| The proposed method of the present invention forms MOSFETs with improved short channel effects and operating speeds over conventional devices. The method for fabricating MOSFETs includes the following steps. At first, isolation regions are formed on a semiconductor substrate and a gate |
| 6358818 |
Method for forming trench isolation regions |
March 19, 2002 |
| The method for forming an isolation region in the present invention mainly includes the following steps. First, a pad layer is formed on a semiconductor substrate and an oxidation masking layer is formed on the pad layer. The oxidation masking layer, the pad layer, and the substrate |
| 6355540 |
Stress-free shallow trench isolation |
March 12, 2002 |
| The present invention proposes a shallow trench isolation region in a semiconductor substrate for ULSI devices. The trench region includes a thermal oxide film formed on the bottom and the sidewall, a CVD dielectric film formed on the bottom of the thermal oxide film, and a channel stop |
| 6348390 |
Method for fabricating MOSFETS with a recessed self-aligned silicide contact and extended source |
February 19, 2002 |
| A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrate. A thermal oxide layer is forme |
| 6342422 |
Method for forming MOSFET with an elevated source/drain |
January 29, 2002 |
| A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. A first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, the first |
| 6331456 |
Fipos method of forming SOI CMOS structure |
December 18, 2001 |
| The present invention discloses a method to form CMOS transistors for high speed and lower power applications. A high energy and low dose phosphorous is implanted in a silicon substrate to fabricate an N-well after a pad oxide layer and a silicon nitride layer is formed. After a thick fi |
| 6329264 |
Method for forming a ragged polysilcon crown-shaped capacitor for a memory cell |
December 11, 2001 |
| In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherei |
| 6323094 |
Method to fabricate deep sub-.mu.m CMOSFETs |
November 27, 2001 |
| The method of the present invention is to fabricate a CMOS device without boron penetration. A nitrided gate oxide and SAS gate electrode are provided to suppress boron penetration. The nitrided gate oxide could be formed in two approaches. One of the approaches is to implant nitrogen |
| 6316316 |
Method of forming high density and low power flash memories with a high capacitive-coupling rati |
November 13, 2001 |
| The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed upon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed over. A portion of the first nitride layer and of the |
| 6303417 |
Method of forming self-aligned planarization twin-well by using fewer mask counts for CMOS trans |
October 16, 2001 |
| The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting |
| 6294797 |
MOSFET with an elevated source/drain |
September 25, 2001 |
| A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the f |
| 6294416 |
Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer |
September 25, 2001 |
| The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting |
| 6284612 |
Process to fabricate ultra-short channel MOSFETs with self-aligned silicide contact |
September 4, 2001 |
| The method of the present invention includes the following steps. First, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A photoresist layer is fo |
| 6281542 |
Flower-like capacitor structure for a memory cell |
August 28, 2001 |
| A structure of a capacitor on a semiconductor wafer including the following structure is disclosed herein. A first electrode including a flower structure is formed on the semiconductor wafer. The first electrode includes a flower neck portion, a flower bottom portion, and a flower top |
| 6274428 |
Method for forming a ragged polysilicon crown-shaped capacitor for a memory cell |
August 14, 2001 |
| In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherei |
| 6268245 |
Method for forming a DRAM cell with a ragged polysilicon crown-shaped capacitor |
July 31, 2001 |
| In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a dynamic random access memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielec |
| 6265263 |
Method for forming a DRAM capacitor with porous storage node and rugged sidewalls |
July 24, 2001 |
| The method for forming a DRAM capacitor can include the following steps. First, a first dielectric layer is formed on a semiconductor substrate, followed by the formation of a second dielectric layer on the first dielectric layer, and the formation of a third dielectric layer on the |
| 6265259 |
Method to fabricate deep sub-.mu.m CMOSFETs |
July 24, 2001 |
| The method of the present invention is to fabricate a CMOS device without boron penetration. Firstly, a gate oxide layer is formed on a semiconductor substrate. A first silicon layer is formed upon the gate oxide layer. Thereafter, a second silicon layer is stacked on the first silic |
| 6259130 |
High density flash memories with high capacitive-couping ratio and high speed operation |
July 10, 2001 |
| The device includes a gate oxide formed on a semiconductor substrate. Oxide regions are respectively formed on the substrate and adjacent to the gate oxide. Textured oxides are formed on the substrate, between the gate oxide and the oxide regions. A floating gate consists of a first poly |
| 6255682 |
Trench DRAM cells with self-aligned field plate |
July 3, 2001 |
| The capacitor includes trenches formed in a semiconductor substrate. Recess portions are formed adjacent to the top portion of the openings of the trenches. An isolation layer is formed on the substrate and on the surface of the recess portions. A first isolation structure is formed on t |
| 6255167 |
Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench fl |
July 3, 2001 |
| A method of fabricating buried bit line flash EEROM cells with shallow trench floating gates for suppressing the short channel effect is disclosed. The method includes the following steps. First, a first polysilicon layer with conductive impurities and a nitride capping layer are seq |
| 6251731 |
Method for fabricating high-density and high-speed nand-type mask roms |
June 26, 2001 |
| The present invention proposes a method for fabricating high-density and high-speed NAND-type mask read-only memories. This method constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-thro |
| 6232648 |
Extended self-aligned crown-shaped rugged capacitor for high density DRAM cells |
May 15, 2001 |
| The present invention disclosed a structure of a self-aligned crown-shaped rugged capacitor for high density DRAM (dynamic random access memory) cells. The crown-shaped rugged capacitor for high density DRAM cells can be formed without the prior art crack issue. One of the advantages of |
| 6214696 |
Method of fabricating deep-shallow trench isolation |
April 10, 2001 |
| The method includes forming a pad oxide, a polysilicon layer over a substrate. Next, an oxide layer is formed over the polysilicon layer. An opening is formed in the oxide layer, the polysilicon layer, and the pad layer. A trench is formed by etching the substrate using the oxide layer |
| 6211556 |
Eliminating buried contact trench in MOSFET devices having self-aligned silicide |
April 3, 2001 |
| A MOSFET device with buried contact structure on a semiconductor substrate has the following major elements with their relative locations. A gate insulator is on a portion of the substrate and a gate electrode is on the gate insulator. A gate sidewall structure is located on sidewalls of |
| 6211016 |
Method for forming high density nonvolatile memories with high capacitive-coupling ratio |
April 3, 2001 |
| A method for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A |
| 6211002 |
CMOS process for forming planarized twin wells |
April 3, 2001 |
| This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as a mask. A thick oxide layer deposited by liquid |
| 6207999 |
Double coding mask read only memory (mask ROM) for minimizing band-to-band leakage |
March 27, 2001 |
| The present invention provides a mask ROM memory to minimize band-to-band leakage. The substrate includes a normal NMOS device region and a NMOS cell region for coding. An isolation region is formed between the normal NMOS device region and the NMOS cell region. A gate oxide layer is for |
| 6207526 |
Method of fabricating an extended self-aligned crown-shaped rugged capacitor for high density DR |
March 27, 2001 |
| The method of the present invention for forming a capacitor on a semiconductor substrate includes the following steps. At first, a first oxide layer is formed over the substrate and a nitride layer is then formed over the oxide layer. A second oxide layer is then formed over the nitr |
| 6207505 |
Method for forming high density nonvolatile memories with high capacitive-coupling ratio |
March 27, 2001 |
| A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A |
| 6204517 |
Single electron transistor memory array |
March 20, 2001 |
| A structure of a single-electron-transistor memory array is disclosed in the present invention. A substrate is provided. A buried oxide layer is on the substrate. A plurality of silicon wires are arranged on the buried oxide layer, wherein each of the silicon wires has a pair of ends. |
| 6204124 |
Method for forming high density nonvolatile memories with high capacitive-coupling ratio |
March 20, 2001 |
| A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A |
| 6190977 |
Method for forming MOSFET with an elevated source/drain |
February 20, 2001 |
| A gate insulator layer is formed over the semiconductor substrate and a first silkcon layer is then formed over the gate insulator layer. An first dielectric layser is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the |
| 6187619 |
Method to fabricate short-channel MOSFETs with an improvement in ESD resistance |
February 13, 2001 |
| A method to fabricate simultaneously a MOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The ESD protective devices are fabricated with a double diffused drain (DDD) junction. In the functional region, a MOSFET structure is characterized as having an |
| 6184087 |
Method for forming high density nonvolatile memories with high capacitive-coupling ratio |
February 6, 2001 |
| A met for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thi |
| 6180988 |
Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure |
January 30, 2001 |
| A MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. Spacers are formed on the substra |
| 6177323 |
Method to form MOSFET with an elevated source/drain for PMOSFET |
January 23, 2001 |
| A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer of the |
| 6171893 |
Method for forming self-aligned silicided MOS transistors with ESD protection improvement |
January 9, 2001 |
| The method of forming MOS transistors includes the following steps. First, isolation regions are formed in the semiconductor substrate to separate the semiconductor substrate into an ESD protective region and a functional region. A gate insulator layer is formed on the substrate and a |
| 6165854 |
Method to form shallow trench isolation with an oxynitride buffer layer |
December 26, 2000 |
| The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A silicon oxynitride film is created near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench |
| 6162681 |
DRAM cell with a fork-shaped capacitor |
December 19, 2000 |
| A method for forming a fork-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first conductive layer (118) over a semiconductor substrate (110), wherein at least a portion of the first doped polysilicon layer communicates to the subst |
| 6156613 |
Method to form MOSFET with an elevated source/drain |
December 5, 2000 |
| A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of th |
| 6156591 |
Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer |
December 5, 2000 |
| The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a pad oxide layer on a semiconductor substrate, an n-well region is defined by implanting a high energy |
| 6153467 |
Method of fabricating high density buried bit line flash EEPROM memory cell with a shallow trenc |
November 28, 2000 |
| A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is succ |
| 6146949 |
Method of manufacturing mask ROM devices with self-aligned coding implant |
November 14, 2000 |
| A method for forming mask read-only memories comprises: A gate oxide layer is formed on a semiconductor substrate. A polysilicon layer is formed on the gate oxide layer. Then, a silicon nitride layer is formed on said polysilicon layer. The gate structures are defined by patterning the |
| 6137152 |
Planarized deep-shallow trench isolation for CMOS/bipolar devices |
October 24, 2000 |
| The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the upper-half trench has a larger width than the lower-half trench. A first insulating layer i |
