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Wu; James
Cheng-Ming) (KaoHsiung, TW
No. of patents:

Patent Number Title Of Patent Date Issued
7482278 Key-hole free process for high aspect ratio gap filling with reentrant spacer January 27, 2009
A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern,
6403416 Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) June 11, 2002
A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO.sub.2) first insula
6365325 Aperture width reduction method for forming a patterned photoresist layer April 2, 2002
A method for fabricating a microelectronic layer. There is first provided a substrate. There is then formed over the substrate a target layer. There is then formed upon the target layer a patterned photoresist layer which defines a first aperture, where the first aperture has a first ape
6323118 Borderless dual damascene contact November 27, 2001
A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process having two etch-stop layers. A first etch-stop layer is formed over a first dielectric layer
6274426 Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure August 14, 2001
A process for fabricating a crown shaped, capacitor structure, in a SAC opening, featuring a silicon nitride spacer, located on the walls of a bottom portion of the SAC opening, has been developed. The process features forming a SAC opening in a thick silicon oxide layer, then repair
6265315 Method for improving chemical/mechanical polish uniformity over rough topography for semiconduct July 24, 2001
A method for making a planar interlevel dielectric (ILD) layer, having improved thickness uniforming across the substrate surface, over a patterned electrically conducting layer is achieved. The method involves forming electrically conducting lines on which is deposited a conformal f
6159786 Well-controlled CMP process for DRAM technology December 12, 2000
A new method of maintaining good control of the dielectric thickness over a top capacitor plate during planarization by CMP by introducing a CMP stop layer under the topmost dielectric layer is described. Semiconductor device structures, including a node contact region, are provided in a
6015733 Process to form a crown capacitor structure for a dynamic random access memory cell January 18, 2000
A process for forming a crown shaped, polysilicon storage node structure, for a DRAM capacitor structure, has been developed. The process features the deposition of a polysilicon layer, on the top surface of a thick insulator layer, as well as on all surfaces of an opening, in the thick
6013550 Method to define a crown shaped storage node structure, and an underlying conductive plug struct January 11, 2000
A process for forming a crown shaped storage node structure, for a DRAM capacitor structure, has been developed. The process features the patterning of a top portion, of a storage node contact plug structure, after patterning of the crown shaped storage node structure, and after remo

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