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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Wu; Hua-Shu
Address:
Hsinchu, TW
No. of patents:
24
Patents:












Patent Number Title Of Patent Date Issued
8278724 Methods of fabricating a micromechanical structure October 2, 2012
Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first pattern
8119992 System for overlay measurement in semiconductor manufacturing February 21, 2012
Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least t
8084361 Semiconductor fabrication method suitable for MEMS December 27, 2011
A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant fil
8049323 Chip holder with wafer level redistribution layer November 1, 2011
A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus e
8012785 Method of fabricating an integrated CMOS-MEMS device September 6, 2011
An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside
7851331 Bonding structures and methods of forming bonding structures December 14, 2010
A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed
7732299 Process for wafer bonding June 8, 2010
The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over
7728396 Semiconductor structures June 1, 2010
A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A par
7696766 Ultra-fine pitch probe card structure April 13, 2010
A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of tips that each comprise a substrate with a conductive via, a first dielectric layer with vias connected to the conductive via, a second dielectric layer with vias over the first d
7582538 Method of overlay measurement for alignment of patterns in semiconductor manufacturing September 1, 2009
A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the l
7468327 Methods of fabricating a micromechanical structure December 23, 2008
Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned
7459344 Method for forming micromachined structure December 2, 2008
The invention provides a method of fabricating a micromachined structure, and in particular to a method of forming a micro-electro-mechanical system (MEMS) structure. A thin silicon cantilevered or suspended structure used to make micromachined structures is first formed from a SOI w
7453127 Double-diffused-drain MOS device with floating non-insulator spacers November 18, 2008
A double-diffused-drain metal-oxide-semiconductor device has a gate structure overlying a semiconductor substrate, a pair of insulator spacers on the sidewalls of the gate structure respectively, and a pair of floating non-insulator spacers embedded in the pair of insulator spacers r
7295374 Micro-lens and micro-lens fabrication method November 13, 2007
A method of manufacturing a micro-lens is disclosed. The method includes providing a convex photoresist surface, forming a lens mold on the convex photoresist surface, removing the lens mold from the convex photoresist surface, forming a micro-lens in the lens mold and removing the m
7255425 Ink-channel wafer integrated with CMOS wafer for inkjet printhead and fabrication method thereof August 14, 2007
An ink-ejection unit of an inkjet printhead integrates an ink-channel wafer onto a CMOS wafer with a heating element fabricated therein. A nozzle film with a nozzle orifice is formed on the backside of the CMOS wafer, which allows two-dimensional ink ejecting from the backside of the
7198975 Semiconductor methods and structures April 3, 2007
A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A par
7094711 Micro pipe manufacturing method August 22, 2006
A method for fabricating micro pipes on a semiconductor wafer or other substrate. According to the method of the invention, a base layer is initially deposited on the substrate and then etched to form a trench which exposes the surface of the substrate. Next, a PR (photoresist) layer
7011933 Method for manufacturing micro-optical mirror arrays March 14, 2006
A method for producing a spheroidal shaped micro-array assembly including providing a substrate having frontside patterned openings formed in the substrate; blanket depositing a photosensitive layer over the substrate including the frontside patterned openings; exposing the photosensitiv
6875689 Method of patterning lines in semiconductor devices April 5, 2005
A new process is provided for the creation of sub-micron conductive lines and patterns. A conductive layer is deposited over the surface of a substrate, a sacrificial layer that differs with the conductive layer in etch characteristics is deposited over the surface of the conductive
6573188 End point detection method for forming a patterned silicon layer June 3, 2003
Within a method for selectively etching a second silicon layer with respect to a first silicon layer upon which is formed the second silicon layer there is employed an etch detection layer interposed between a first region of the first silicon layer and the second silicon layer, but not
6534405 Method of forming a MOSFET device featuring a dual salicide process March 18, 2003
A method for fabricating a MOSFET device using a dual salicide formation procedure has been developed. The process features a first salicide formation procedure used to create a thick metal silicide component for a composite gate structure, with the composite gate structure in turn c
6489237 Method of patterning lines in semiconductor devices December 3, 2002
A new process is provided for the creation of sub-micron conductive lines and patterns. A conductive layer is deposited over the surface of a substrate, a sacrificial layer that differs with the conductive layer in etch characteristics is deposited over the surface of the conductive
6187668 Method of forming self-aligned unlanded via holes February 13, 2001
The present invention discloses a method of forming self-aligned unlanded via holes. First, a substrate having a patterned conductive layer on its surface is provided, and then a first dielectric layer is deposited on the substrate by using high density plasma chemical vapor deposition (
6080674 Method for forming via holes June 27, 2000
A method for forming a plurality of self-aligned via holes applied to a semiconductor device is disclosed. The method includes steps of (a) providing a substrate forming thereon a conducting layer forming thereon a sacrificial layer; (b) partially removing the sacrificial layer while










 
 
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