| Patent Number |
Title Of Patent |
Date Issued |
| 7577794 |
Low latency coherency protocol for a multi-chip multiprocessor system |
August 18, 2009 |
| Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and pr |
| 7475190 |
Direct access of cache lock set data without backing memory |
January 6, 2009 |
| Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this porti |
| 7355601 |
System and method for transfer of data between processors using a locked set, head and tail poin |
April 8, 2008 |
| A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includ |
| 7305524 |
Snoop filter directory mechanism in coherency shared memory system |
December 4, 2007 |
| Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to |
| 6791352 |
Method and apparatus for debugging a chip |
September 14, 2004 |
| In a first aspect, an apparatus is provided that is adapted to multiplex debug signals of an integrated circuit. The apparatus includes at least a first multiplexing circuit and a second multiplexing circuit. The first multiplexing circuit is adapted to receive first debug signals from t |
| 6134699 |
Method and apparatus for detecting virtual address parity error for a translation lookaside buff |
October 17, 2000 |
| A method and apparatus are provided for detecting virtual address parity error for a translation lookaside buffer in a computer system. The computer system includes a processor unit, a cache coupled to the processor unit, a main memory, and a storage control unit including a translat |
| 6044447 |
Method and apparatus for communicating translation command information in a multithreaded enviro |
March 28, 2000 |
| A method and apparatus are provided for communicating translation command information in a multithreaded environment in a computer system. The computer system includes a processor unit, an instruction unit coupled to the processor unit, a cache coupled to the processor unit, a main memor |
