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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Wong; Robert C.
Address:
Poughkeepsie, NY
No. of patents:
46
Patents:












Patent Number Title Of Patent Date Issued
8178945 Programmable PN anti-fuse May 15, 2012
Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p- substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p- substrate; forming a resist mask ov
8173532 Semiconductor transistors having reduced distances between gate electrode regions May 8, 2012
A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top
8099688 Circuit design January 17, 2012
A design process includes inputting a design file representing a circuit design embodied in a non-transitory computer-readable medium, and using a computer to translate the circuit design into a netlist. The netlist comprises a representation of a plurality of wires, transistors, and
8035126 One-transistor static random access memory with integrated vertical PNPN device October 11, 2011
A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PN
7915691 High density SRAM cell with hybrid devices March 29, 2011
Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the
7875544 Method of producing a semiconductor interconnect architecture including generation of metal hole January 25, 2011
A reduction in the intersection of vias on the last layer ("VL") and holes in the last thin metal layer ("MLHOLE") can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of inter
7859044 Partially gated FINFET with gate dielectric on only one sidewall December 28, 2010
A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the
7781797 One-transistor static random access memory with integrated vertical PNPN device August 24, 2010
A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PN
7768816 SRAM cell design to improve stability August 3, 2010
A design structure embodied in a machine readable medium for use in a design process, the design structure representing a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment,
7738283 Design structure for SRAM active write assist for improved operational margins June 15, 2010
A design structure embodied in a machine-readable medium used in a design process is provided. The design structure comprises a static random access memory ("SRAM"), including a plurality of cells arranged in an SRAM having a plurality of columns; and a voltage control circuit operab
7732872 Integration scheme for multiple metal gate work function structures June 8, 2010
A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first
7728392 SRAM device structure including same band gap transistors having gate stacks with high-K dielect June 1, 2010
An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k
7678658 Structure and method for improved SRAM interconnect March 16, 2010
A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned p
7586806 SRAM active write assist method for improved operational margins September 8, 2009
A method is provided for controlling a voltage level supplied to a static random access memory ("SRAM"). In such method, when a column of the SRAM is selected for writing, a first p-type field effect transistor ("PFET") and a second PFET can be operated to supply the power at a lower vol
7515489 SRAM having active write assist for improved operational margins April 7, 2009
A static random access memory (SRAM) is provided which includes a plurality of columns and a plurality of cells arranged therein. A voltage control circuit can be used to temporarily reduce a voltage at which power is supplied to cells belonging to a column selected for a write opera
7466604 SRAM voltage control for improved operational margins December 16, 2008
A static random access memory ("SRAM") is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each
7355906 SRAM cell design to improve stability April 8, 2008
A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL)
7313032 SRAM voltage control for improved operational margins December 25, 2007
A static random access memory ("SRAM") is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of c
7283410 Real-time adaptive SRAM array for high SEU immunity October 16, 2007
A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff
7188321 Generation of metal holes by via mutation March 6, 2007
A reduction in the intersection of vias on the last layer ("VL") and holes in the last thin metal layer ("MLHOLE") can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of inter
6958516 Discriminative SOI with oxide holes underneath DC source/drain October 25, 2005
A selective SOI structure having body contacts for all the devices while excluding the buried oxide that is directly underneath diffusions of DC nodes such as applied voltage Vdd, ground GND, reference voltage Vref, and other like DC nodes is provided. The selective SOI structure of the
6888741 Secure and static 4T SRAM cells in EDRAM technology May 3, 2005
Disclosed herein is a 4T (four transistor) SRAM cells. Stability, fabrication and integration density advantages as well as a high degree of soft error immunity with small and potentially tailorable write delay penalty may potentially be available in a memory cell by providing a sour
6876040 Dense SRAM cells with selective SOI April 5, 2005
A SRAM cell fabricated in SSOI (selective silicon on insulator) comprises cross coupled PFET pull-up devices P1, P2 and NFET pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply and the N1, N2 devices being connected to the ground. A first passgate NL is
6856031 SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD February 15, 2005
A low cost SRAM (Static Random Access Memory) cell is disclosed with P well and N well contacts and preferably with a P+ diffusion crossing to ground. The SRAM cell is complete at the M2 metal level and has improved cell passgate leakage, functionality and fabrication yields. The SRAM ce
6834003 Content addressable memory with PFET passgate SRAM cells December 21, 2004
A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power diss
6751151 Ultra high-speed DDP-SRAM cache June 15, 2004
An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the
6654277 SRAM with improved noise sensitivity November 25, 2003
A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low .beta. ratio for high performance. A second portion of the array contains SRAM cells with a higher .beta. ratio that a
6552941 Method and apparatus for identifying SRAM cells having weak pull-up PFETs April 22, 2003
A method for determining the memory cell stability of individual memory cells included within a memory array is disclosed. In an exemplary embodiment, the method includes presetting each memory cell to a first logic state and then applying a gradually increasing, controlled leakage c
6549453 Method and apparatus for writing operation in SRAM cells employing PFETS pass gates April 15, 2003
A method for preparing a computer memory cell for a data write operation thereto is disclosed. The memory cell has a cell supply voltage source which is connected at one end to pull-up devices within the memory cell, and is connected at an opposite end to pull-down devices within the mem
6507511 Secure and dense SRAM cells in EDRAM technology January 14, 2003
Addition of capacitance to the storage nodes of static random access memory cells and other types of integrated circuits substantially increases Q.sub.crit and substantially eliminates soft errors due to alpha particles; susceptibility to which would otherwise increase as integrated
6461877 Variable data compensation for vias or contacts October 8, 2002
Described herein is a method for selectively enlarging vias connecting two different layers of conductors in a semiconductor device. Whether or not an individual via is extended on each of its edges is determined by the distance of the edge to the neighboring features. Since many vias ca
6341083 CMOS SRAM cell with PFET passgate devices January 22, 2002
A CMOS SRAM cell provided with PFET devices as passgate transistors is described to reduce the surface area taken by the pull-up and pull-down devices. A six-transistor, single-port SRAM cell is shown to dissipate 75% less power when compared to conventional cells, and its cell stability
6256755 Apparatus and method for detecting defective NVRAM cells July 3, 2001
An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first charac
5681770 Process for making and programming a flash memory array October 28, 1997
A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain regio
5672892 Process for making and programming a flash memory array September 30, 1997
A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain regio
5654917 Process for making and programming a flash memory array August 5, 1997
A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain regio
5541130 Process for making and programming a flash memory array July 30, 1996
A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain regio
5365117 Logic gates having fast logic signal paths through switchable capacitors November 15, 1994
Switchable diffused junction capacitors providing selectable data signal paths in a logic gate. A control circuit, such as a current switch, renders one of the junction capacitors conductive to present a large diffusion capacitance which acts as a fast signal pathway to the respectiv
5297089 Balanced bit line pull up circuitry for random access memories March 22, 1994
A balancing circuit which may be used as part of a random access memory system for eliminating bit line offset, is disclosed. The balancing circuit contemplated by the invention is capable of supporting rapid memory accesses (such as reads when the memory enters a "read" mode); and s
5276638 Bipolar memory cell with isolated PNP load January 4, 1994
A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to both load transistors, are c
5255240 One stage word line decoder/driver with speed-up Darlington drive and adjustable pull down October 19, 1993
A word line decoder/driver has a Darlington circuit connected in parallel with word line driver transistors to provide rapid switching thereof. The Darlington circuit receives an input from decoder transistors through a capacitance, such as a diffusion capacitance, which establishes a ti
5210447 Word decoder with SBD-T.sub.x clamp May 11, 1993
An anti-saturation clamp for a word decoder utilizes a Schottky Barrier Diode (SBD) S.sub.x in combination with a transistor T.sub.x. The transistor T.sub.x is in circuit with a switching transistor T and diverts the majority of pull down current from the switching transistor. The sa
5124573 Adjustable clock chopper/expander circuit June 23, 1992
A clock chopper/expander circuit 10 includes a reset dominant latch circuit 20 which is set by a CLOCK IN signal 12 and reset by a delayed CLOCK IN signal labelled DELAY 26, provided by an asymmetrical delay circuit 22 which delays the CLOCK IN signal T.sub.D seconds. The delay circuit 2
5120987 Tunable timer for memory arrays June 9, 1992
The present invention is directed to a tunable delay element incorporating one-half of a bipolar SRAM cell and a reference generator. In operation, the rising edge and incoming clock pulse sets the receiver/latch, latching the internal clock (i.e., the write pulse). The same rising edge
4922455 Memory cell with active device for saturation capacitance discharge prior to writing May 1, 1990
A transistor memory cell is disclosed of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data. The cell is equipped with controlled active devices for discharging the saturati
4813017 Semiconductor memory device and array March 14, 1989
A memory array fabricated on a silicon substrate consists of memory cells each having two lateral p-n-p load-injector transistors and two vertical n-p-n flip-flop transistors with the p-n-p's being formed in a portion of the substrate which is electrically isolated from portions of the










 
 
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