| Patent Number |
Title Of Patent |
Date Issued |
| 8298882 |
Metal gate and high-K dielectric devices with PFET channel SiGe |
October 30, 2012 |
| Fabricating of semiconductor devices includes: depositing epitaxially a SiGe layer onto both NFET and PFET portions of a Si surface; blanket disposing a first sequence of layers over the SiGe layer including a high-k dielectric and a metal, incorporating the first sequence of layers |
| 8298385 |
Method and apparatus for forming nickel silicide with low defect density in FET devices |
October 30, 2012 |
| A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is f |
| 8288276 |
Method of forming an interconnect structure including a metallic interfacial layer located at a |
October 16, 2012 |
| Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first |
| 8288217 |
Stressor in planar field effect transistor device |
October 16, 2012 |
| A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal |
| 8268689 |
Multiple threshold voltages in field effect transistor devices |
September 18, 2012 |
| A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting cha |
| 8183145 |
Structure and methods of forming contact structures |
May 22, 2012 |
| Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; dep |
| 8138041 |
In-situ silicon cap for metal gate electrode |
March 20, 2012 |
| Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is |
| 8133810 |
Structure for metal cap applications |
March 13, 2012 |
| An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect struc |
| 8129842 |
Enhanced interconnect structure |
March 6, 2012 |
| The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can |
| 8120144 |
Method for forming dual high-K metal gate using photoresist mask and structures thereof |
February 21, 2012 |
| Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photores |
| 8105937 |
Conformal adhesion promoter liner for metal interconnects |
January 31, 2012 |
| A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is fo |
| 8095230 |
Method for optimizing the routing of wafers/lots based on yield |
January 10, 2012 |
| A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for incre |
| 8084346 |
Replacement metal gate method |
December 27, 2011 |
| A method includes forming a dummy gate in a dielectric layer on a substrate, the dummy gate including a sacrificial oxide layer and a dummy gate body over the sacrificial oxide layer; removing the dummy gate body resulting in a gate opening with the sacrificial oxide layer in a bottom |
| 8053317 |
Method and structure for improving uniformity of passive devices in metal gate technology |
November 8, 2011 |
| Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers |
| 8023305 |
High density planar magnetic domain wall memory apparatus |
September 20, 2011 |
| A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further |
| 8009453 |
High density planar magnetic domain wall memory apparatus |
August 30, 2011 |
| A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further |
| 7999323 |
Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS d |
August 16, 2011 |
| The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least |
| 7973409 |
Hybrid interconnect structure for performance improvement and reliability enhancement |
July 5, 2011 |
| The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure inc |
| 7960276 |
Conductor-dielectric structure and method for fabricating |
June 14, 2011 |
| A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating |
| 7943474 |
EDRAM including metal plates |
May 17, 2011 |
| A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. An upper electrode is then forme |
| 7923712 |
Phase change memory element with a peripheral connection to a thin film electrode |
April 12, 2011 |
| A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element |
| 7915115 |
Method for forming dual high-k metal gate using photoresist mask and structures thereof |
March 29, 2011 |
| Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photores |
| 7902061 |
Interconnect structures with encasing cap and methods of making thereof |
March 8, 2011 |
| A method of making an interconnect structure: which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric material; and depositing an enca |
| 7867895 |
Method of fabricating improved interconnect structure with a via gouging feature absent profile |
January 11, 2011 |
| An interconnect structure including a gouging feature at the bottom of the via openings and a method of forming the same, which does not introduce either damages caused by Ar sputtering into the dielectric material that includes the via and line openings, nor plating voids into the struc |
| 7851885 |
Methods and systems involving electrically programmable fuses |
December 14, 2010 |
| An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse. |
| 7851321 |
Semiconductor integrated circuit devices having high-Q wafer back-side capacitors |
December 14, 2010 |
| Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes |
| 7838908 |
Semiconductor device having dual metal gates and method of manufacture |
November 23, 2010 |
| A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermed |
| 7838873 |
Structure for stochastic integrated circuit personalization |
November 23, 2010 |
| A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the |
| 7808082 |
Structure and method for dual surface orientations for CMOS transistors |
October 5, 2010 |
| The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that pre |
| 7772119 |
Dual liner capping layer interconnect structure |
August 10, 2010 |
| A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angst |
| 7759741 |
Method and apparatus for forming nickel silicide with low defect density in FET devices |
July 20, 2010 |
| A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is f |
| 7754594 |
Method for tuning the threshold voltage of a metal gate and high-k device |
July 13, 2010 |
| A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on |
| 7750418 |
Introduction of metal impurity to change workfunction of conductive electrodes |
July 6, 2010 |
| Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer |
| 7749890 |
Low contact resistance metal contact |
July 6, 2010 |
| A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region. |
| 7737026 |
Structure and method for low resistance interconnections |
June 15, 2010 |
| A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten |
| 7727890 |
High aspect ratio electroplated metal feature and method |
June 1, 2010 |
| Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids |
| 7726010 |
Method of forming a micro-electromechanical (MEMS) switch |
June 1, 2010 |
| A method of fabricating a MEMS switch having a free moving inductive element within in micro-cavity guided by at least one inductive coil. The switch consists of an upper inductive coil at one end of a micro-cavity; optionally, a lower inductive coil; and a free-moving inductive element |
| 7709960 |
Dual liner capping layer interconnect structure |
May 4, 2010 |
| A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angst |
| 7691701 |
Method of forming gate stack and structure thereof |
April 6, 2010 |
| Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated |
| 7659199 |
Air break for improved silicide formation with composite caps |
February 9, 2010 |
| Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is f |
| 7635884 |
Method and structure for forming slot via bitline for MRAM devices |
December 22, 2009 |
| A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the s |
| 7622386 |
Method for improved formation of nickel silicide contacts in semiconductor devices |
November 24, 2009 |
| A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400.degree. C., transferring the semiconductor wafer from a degas chamber to a depositio |
| 7598545 |
Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS d |
October 6, 2009 |
| The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one |
| 7585765 |
Formation of oxidation-resistant seed layer for interconnect applications |
September 8, 2009 |
| An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen |
| 7576003 |
Dual liner capping layer interconnect structure and method |
August 18, 2009 |
| A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angst |
| 7566651 |
Low contact resistance metal contact |
July 28, 2009 |
| A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region. |
| 7557424 |
Reversible electric fuse and antifuse structures for semiconductor devices |
July 7, 2009 |
| A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features; conformally depos |
| 7544608 |
Porous and dense hybrid interconnect structure and method of manufacture |
June 9, 2009 |
| A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over th |
| 7544578 |
Structure and method for stochastic integrated circuit personalization |
June 9, 2009 |
| A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the |
| 7531407 |
Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of f |
May 12, 2009 |
| Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backsi |
