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Willis; Donald H.
Indianapolis, IN
No. of patents:

1 2

Patent Number Title Of Patent Date Issued
7398005 Trick mode playback of recorded video July 8, 2008
The present invention concerns a method (200) and system (100) for producing a trick mode playback of a segment of video containing a plurality of predictive pictures. The invention includes the steps of: (a) decoding (212) a portion of a predictive picture from the plurality of pred
7376341 Modifying video signals by converting non-intra pictures May 20, 2008
The invention concerns a method (200) and system (10) for recording onto a storage medium (26) a video segment. The method includes the steps of: receiving the video segment (210) in which the video segment contains at least one predictive picture; and selectively converting the at least
5633689 Apparatus for separating a digital composite video signal into components May 27, 1997
A digital filter (20,30) separates an M-bit (12) chrominance component (C12) from an N-bit (8) digital composite video signal (CV) supplied thereto, M (12) being greater than N (8) due to arithmetic operations (24,44,46,50) required for the separation. The separated M bit chrominance
5565928 Circuit for generating a scan at a multiple of a synchronizing signal October 15, 1996
In a synchronizing circuit, an oscillator provides an output signal at a frequency that is a higher integral multiple than that of a synchronizing input signal. A control circuit, responsive to the input signal and a feedback signal representative of the output signal, generates a contro
5519454 Luma/chroma separation filter with common delay element for comb filter separation and recursive May 21, 1996
A composite video input signal is combined with a noise reduction signal to form a noise reduced first video signal which is delayed by multiple time periods of (i) one line less one-half color cycle, (ii) one line and (iii) one line plus one-half color cycle to form respective ones of f
5442406 Wide screen television August 15, 1995
A video display has a first format display ratio. A mapping circuit maps an adjustable picture display are on the video display. A signal processor generates first and second video signals from input video signals having one of different format display ratios. A switching circuit selecti
5434625 Formatting television pictures for side by side display July 18, 1995
A video display system comprising: a first source of a first video signal representative of a first picture having a first display format ratio; a first memory having write and read ports, the first video signal being written into the first memory at a slower rate than the first video si
5430494 Independent horizontal panning for side-by-side pictures July 4, 1995
A video display system comprises: a video display; first and second signal processors for cropping first and second video signals representative of first and second pictures; a circuit for generating a side-by-side display format of the pictures on the video display; and, a panning contr
5374963 Picture resolution enhancement with dithering and dedithering December 20, 1994
A dithering technique in accordance with an inventive arrangement saves two bits per sample in a wideband video signal. In accordance with this arrangement, a dither signal is added to an n-bit video signal. The adder should include a limiter to avoid overflows. The samples are truncated
5365278 Side by side television pictures November 15, 1994
A video display system comprises analog to digital converters for quantizing first and second video signals, representing first and second pictures respectively, at higher and lower levels of quantization resolution relative to one another. The analog to digital converters can operat
5329369 Asymmetric picture compression July 12, 1994
A wide screen television apparatus comprises a video display having a first format display ratio of width to height, for example approximately 16.times.9. A first video signal defines a first picture. A second video signal defines a second picture in a second format display ratio of widt
5309234 Adaptive letterbox detector May 3, 1994
A video display control system automatically controls a video display responsive to detection of letterbox format input video signals having varying format display ratios. A detection circuit continuously detects the first and last lines of active video in a video signal. A memory st
5249049 Managing letterbox displays September 28, 1993
A video display control system, comprises a video display having a first format display ratio. A picture height circuit determines an active video picture height from an input video signal having a second format display ratio. A detector circuit identifies letterbox formats responsive to
5175619 Progressive scan television system using luminance low frequencies from previous field December 29, 1992
A progressive scan processor includes an input circuit which produces a video difference signal representative of a difference between a first low frequency component derived from a current line of a video input signal and a second low frequency component derived by motion adaptive proce
5162910 Synchronizing circuit November 10, 1992
A phase locked loop circuit regenerates a synchronizing signal. A first counter counts adjustable and fixed time intervals. A flip/flop generates synchronizing pulses having periods defined by sets of the adjustable and fixed time intervals. A second counter successively measures phase
4992874 Method and apparatus for correcting timing errors as for a multi-picture display February 12, 1991
A picture-in-a-picture television receiver displays a compound image which includes a compressed image derived from an auxiliary signal inset in a full-size image derived from a main signal. The auxiliary composite video signal is sampled synchronous with a system clock signal that is bu
4987493 Memory efficient interlace apparatus and method as for a picture in a picture display January 22, 1991
A picture-in-a-picture television receiver includes a memory for holding samples representing a vertically and horizontally compressed image. The memory is divided into three parts, a main portion which holds one field of the compressed image and first and second crossover buffers, each
4882626 Signal combining circuitry November 21, 1989
A signal combining circuit for adaptively combining first and second signals includes a comparator to develop a control signal to indicate when the combination of the first and second signals will have an amplitude exceeding a predetermined amplitude in one polarity sense. In the absence
4802000 Video switching apparatus having interference prevention feature January 31, 1989
A Y/C selector switch is coupled to receive a first pair of internally-separated component signals Y.sub.1, C.sub.1 in addition to a second and a third pair of externally-supplied wideband component signals Y.sub.2, C.sub.2 and Y.sub.3, C.sub.3. The switch selects one of the pairs of
4789960 Dual port video memory system having semi-synchronous data input and data output December 6, 1988
A dual port video memory system includes a serial-to-parallel converter coupled to the input data port and a parallel-to-serial converter coupled to the output data port. Four-bit pixel values are clocked into the serial-to-parallel converter synchronous with an input clock signal and
4786963 Adaptive Y/C separation apparatus for TV signals November 22, 1988
An adaptive luma/chroma separation apparatus is herein disclosed. Means, including delay elements and bandpass filters, are employed to generate a set of three bandpassed signals B.sub.b, M.sub.b and T.sub.b, which are delayed with respect to each other by one horizontal line period. A
4782391 Multiple input digital video features processor for TV signals November 1, 1988
A video features processor for use with a display device includes a first clock that is line locked to the display and a skew-shifted second clock that is phase locked to the horizontal sync component of an auxiliary video signal. An A/D converter, responsive to the skew-shifted clock,
4761686 TV receiver having freeze field display August 2, 1988
An interpolating apparatus for generating a pair of non-identical, interlaced fields from a single stored field of video signal. One of the interlaced fields is generated by adding three-fourths of one line's amplitude to one-fourth of the next line's amplitude. The other interlaced
4750039 Circuitry for processing a field of video information to develop two compressed fields June 7, 1988
A picture-within-a-picture television receiver includes circuitry for displaying a reduced-size frozen image developed from an auxiliary signal as an inset in the main image. To develop signals representing two fields of the compressed auxiliary image, the system includes circuitry which
4703341 Television having luma/chroma separation apparatus October 27, 1987
A frame comb filter includes a pair of serially-connected field memories. In the normal display mode, the first field memory stores one field of incoming composite video signal CVS and provides a field delayed video signal FDS. The second field memory stores one field of the field delaye
4701785 Frame comb filter having freeze frame feature October 20, 1987
A combination frame comb/freeze frame apparatus is disclosed. In the normal mode, the apparatus serves to separate one of the component signals (luma or chroma) from a composite video signal. In the freeze frame mode, the separated component signal is stored in the frame store, and repea
4682085 Gullwing distortion corrected deflection circuitry for a square-planar picture tube July 21, 1987
Line and field deflection circuits generate line and field deflection currents in respective line and field deflection windings to scan a raster on the phosphor screen of a square-planar picture tube having an aspherical faceplate. The asphericity of the faceplate subjects the scanne
4680632 Television display system with flicker reduction processor having burst locked clock and skew co July 14, 1987
A speed-up memory doubles the field rate of a video input signal by repeating each field to reduce flicker when the double field rate signal is displayed. Read/write clocks for controlling the memory are locked to the color subcarrier of the video input signal thereby tending to produce
4672642 Circuit for generating a clock signal at an AC line frequency June 9, 1987
A periodic signal, at the frequency of the AC mains supply voltage, contains signal pulses, each having a duration that is substantially shorter than half the period of the AC mains supply voltage. The periodic signal is coupled to a high frequency transformer to form a periodic outp
4667240 Timing correction circuitry as for TV signal recursive filters May 19, 1987
In memory-based video signal processing systems such as frame recursive filters, for example, system performance is dependent upon critical timing relationships between incoming signals and delayed signals produced from the memory. Video signal from various sources, e.g. VTR's, tend to h
4647968 Analog-to-digital conversion system as for a narrow bandwidth signal processor March 3, 1987
A narrow bandwidth analog-to-digital conversion (ADC) system is described in the context of the color burst processing and burst phase detecting circuitry of a digital color television receiver. The ADC includes a dither generator which adds a dither signal to either the analog input
4646138 Video signal recursive filter with luma/chroma separation February 24, 1987
A motion adaptive recursive filter is modified to separate luminance or chrominance signal from composite video. The filter proportions and sums current and frame delayed signal recursively to provide signal-to-noise enhanced luminance signal with the chrominance component reduced to a
4645990 High voltage control circuit for video display apparatus February 24, 1987
A horizontal deflection circuit output stage is coupled to a first end terminal of a primary winding of a flyback transformer for developing at that terminal a retrace voltage. A second end terminal of the primary winding is coupled to a switched mode power supply that provides at the
4639780 Television synchronizing apparatus January 27, 1987
In a synchronized digital horizontal deflection system generating at 2xf.sub.H, a first word is produced that is indicative of the length of one-half the period H between f.sub.H rate horizontal sync pulses. A first f.sub.H rate signal that is synchronized to the horizontal sync pulses i
4638360 Timing correction for a picture-in-picture television system January 20, 1987
System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, ten
4636861 Two-loop line deflection system January 13, 1987
In a synchronized digital horizontal deflection system operating at 2.times.f.sub.H, a digital phase-lock-loop circuit generates first f.sub.H rate signal that is synchronized to the horizontal sync pulses, and a second f.sub.H rate second signal that is delayed from the first signal by
4633320 Video signal processor with automatic kinescope beam current limiter December 30, 1986
In a digital video signal processing system including an image reproducing kinescope and a digital-to-analog converter (DAC), excessive kinescope beam current are automatically limited in response to a control signal which varies a reference voltage for the DAC such that the peak-to-peak
4630294 Digital sample rate reduction system December 16, 1986
A digital sample rate reduction apparatus receives an input signal occurring at a given sample rate and produces an output signal occurring at a rate which is two-thirds the input sample rate. One half of the output samples are interpolated samples and the other half are original inp
4625154 Deflection circuit with a switched mode modulator circuit November 25, 1986
A trace switch, operated at a line rate, is coupled to a line deflection winding and a trace capacitance for applying a trace voltage to the deflection winding to generate line scanning current in the deflection winding. A deflection retrace capacitance is coupled to the deflection w
4623913 Progressive scan video processor November 18, 1986
A digital video signal processing circuit generates interlaced luminance and chrominance signals from interlaced composite color video signals. The interlaced luminance signal contains vertical detail information without peaking. Each of two progressive scan speed-up processors, controll
4602276 Digital signal level overload system July 22, 1986
A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated
4599642 Video signal processor with bias error compensation July 8, 1986
A color television receiver with luminance and chrominance signal channels includes an automatic kinescope beam current limiter, an automatic white level drive control network, and an automatic black level bias control network. A switching network is timed to operate such that a control
4595953 Television receiver having character generator with burst locked pixel clock and correction for June 17, 1986
A television receiver includes a character generator for producing alphanumeric data or graphic symbols to be displayed along with a received video signal. An oscillator, locked to a multiple of the color subcarrier frequency of the video signal, supplies a clock signal to the character
4594726 Dedithering circuitry in digital TV receiver June 10, 1986
A 7 bit digital signal is dithered by adding a low-level digital dithering signal comprised of alternating 1's and 0's, and by truncating the product to 6 bits. To dedither, an EXCLUSIVE-OR gate compares the previous and the current values of the least significant bit of the 6 bit dither
4593315 Progressive scan television receiver for non-standard signals June 3, 1986
Plural phase detectors in a progressively scanned television receiver measure the phase of the receiver video speed-up memory read and write clocks with respect to the double line-rate horizontal sweep signal of the display. Delay means are provided for delaying the video signal recovere
4591832 Digital-to-analog conversion system as for use in a digital TV receiver May 27, 1986
A digital-to-analog converter system includes two DAC's operated in ping pong fashion with their analog output signals linearly summed. To preclude bandwidth limiting inherent in the summing operation the applied digital input signal is preconditioned in accordance with the transfer func
4558351 Hue correction circuit for a digital TV receiver December 10, 1985
A digital hue correction circuit for correcting the color of digital TV chrominance signals includes a pipelined divider arranged to divide the smaller of the magnitudes of I and Q color mixture signals by the larger of the magnitudes of the I and Q signals to produce quotients represent
4556900 Scaling device as for quantized B-Y signal December 3, 1985
A signal processing apparatus includes a scaling device for increasing the magnitude of a signal from a source to better use the dynamic range of processing apparatus, and to reduce the effects of noise and error sources. This is particularly useful in a television receiver where the
4554578 Error compensated control system in a video signal processor November 19, 1985
A color television receiver with luminance and chrominance signal channels includes an automatic kinescope beam current limiter, an automatic white level drive control network, and an automatic black level bias control network. A switching network is timed to operate such that a control
4543599 Analog-to-digital conversion apparatus including double dither signal sources September 24, 1985
Digital representations of analog signals are limited in resolution accuracy by the number of bits in the digital output signal of an analog-to-digital converter which limits the number of analog output levels produceable by a digital-to-analog converter. The apparent resolution accu
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