| Patent Number |
Title Of Patent |
Date Issued |
| 7222064 |
Instruction processor emulation having inter-processor messaging accounting |
May 22, 2007 |
| Techniques are described for emulating inter-processor communications between multiple instruction processors. The techniques provide inter-processor message accounting and error detection. A system, for example, includes software executing within an emulation environment provided by |
| 7096322 |
Instruction processor write buffer emulation using embedded emulation control instructions |
August 22, 2006 |
| Techniques are described for accurately and efficiently emulating an instruction processor having a write buffer. The described techniques may be utilized to quickly develop an emulated instruction processor that provides a fully-functional write buffer interface in an efficient and |
| 7065614 |
System and method for maintaining memory coherency within a multi-processor data processing syst |
June 20, 2006 |
| The current invention provides a system and method for maintaining memory coherency within a multiprocessor environment that includes multiple requesters such as instruction processors coupled to a shared main memory. Within the system of the current invention, data may be provided f |
| 6993630 |
Data pre-fetch system and method for a cache memory |
January 31, 2006 |
| A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines |
| 6976128 |
Cache flush system and method |
December 13, 2005 |
| A system and method is provided to selectively flush data from cache memory to a main memory irrespective of the replacement algorithm that is used to manage the cache data. According to one aspect of the invention, novel "page flush" and "cache line flush" instructions are provided to f |
| 6973541 |
System and method for initializing memory within a data processing system |
December 6, 2005 |
| An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a "page zero" instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, |
| 6934810 |
Delayed leaky write system and method for a cache memory |
August 23, 2005 |
| A mechanism to selectively leak data signals from a cache memory is provided. According to one aspect of the invention, an Instruction Processor (IP) is coupled to generate requests to access data signals within the cache. Some requests include a leaky designator, which is activated |
