| Patent Number |
Title Of Patent |
Date Issued |
| 7568076 |
Variable store gather window |
July 28, 2009 |
| A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a |
| 7543120 |
Processor and data processing system employing a variable store gather window |
June 2, 2009 |
| A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a |
| 7536288 |
Method, system and program product supporting user tracing in a simulator |
May 19, 2009 |
| According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generat |
| 7533227 |
Method for priority scheduling and priority dispatching of store conditional operations in a sto |
May 12, 2009 |
| A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit |
| 7529655 |
Program product for defining and recording minimum and maximum event counts of a simulation util |
May 5, 2009 |
| According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation mod |
| 7519524 |
Program product for providing a configuration specification language supporting incompletely spe |
April 14, 2009 |
| In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective plurality of different possibl |
| 7500065 |
Data processing system and method for efficient L3 cache directory management |
March 3, 2009 |
| A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the |
| 7493446 |
System and method for completing full updates to entire cache lines stores with address-only bus |
February 17, 2009 |
| A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable |
| 7493417 |
Method and data processing system for microprocessor communication using a processor interconnec |
February 17, 2009 |
| Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel |
| 7490202 |
Data processing system and method for efficient L3 cache directory management |
February 10, 2009 |
| A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the |
| 7480772 |
Data processing system and method for efficient communication utilizing an Tn and Ten coherency |
January 20, 2009 |
| A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache m |
| 7480608 |
Method and system for reducing storage requirements of simulation data via KEYWORD restrictions |
January 20, 2009 |
| Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list associated with the HDL model is received. The HDL model has a maximum number of possib |
| 7469400 |
Method, system and program product supporting presentation of a simulated or hardware system inc |
December 23, 2008 |
| Within a display device, a respective one of a plurality of design graphical representations is displayed for each of a plurality of hierarchically arranged design entity instances within a simulated system. The design entity instances include a particular design entity instance cont |
| 7454737 |
Method, system and program product for specifying and using register entities to configure a sim |
November 18, 2008 |
| In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. W |
| 7454577 |
Data processing system and method for efficient communication utilizing an Tn and Ten coherency |
November 18, 2008 |
| A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache m |
| 7454325 |
Method, system and program product for defining and recording threshold-qualified count events o |
November 18, 2008 |
| According to one method of simulation processing, a count event counter for a count event is created within instrumentation of a hardware description language (HDL) simulation model of a design and a threshold greater than 1 is established for the count event counter. The design is t |
| 7426461 |
Method, system and program product for providing a configuration specification language supporti |
September 16, 2008 |
| In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective plurality of different possibl |
| 7409504 |
Chained cache coherency states for sequential non-homogeneous access to a cache line with outsta |
August 5, 2008 |
| A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate |
| 7395524 |
Method, system and program product providing a configuration specification language having clone |
July 1, 2008 |
| Methods, data processing systems, and program products supporting the insertion of clone latches within a digital design are disclosed. According to one method, a parent latch within the digital design is specified in an HDL statement in one of the HDL files representing a digital de |
| 7392501 |
Method, system and program product providing a configuration specification language supporting a |
June 24, 2008 |
| A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at |
| 7392169 |
Method, system and program product for defining and recording minimum and maximum event counts o |
June 24, 2008 |
| According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation mod |
| 7389490 |
Method, system and program product for providing a configuration specification language supporti |
June 17, 2008 |
| In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statem |
| 7386825 |
Method, system and program product supporting presentation of a simulated or hardware system inc |
June 10, 2008 |
| Within a display device, a respective one of a plurality of design graphical representations is displayed for each of a plurality of hierarchically arranged design entity instances within a simulated system. The design entity instances include a particular design entity instance cont |
| 7373290 |
Method and system for reducing storage requirements of simulation data via keyword restrictions |
May 13, 2008 |
| Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list associated with the HDL model is received. The HDL model has a maximum number of possib |
| 7370155 |
Chained cache coherency states for sequential homogeneous access to a cache line with outstandin |
May 6, 2008 |
| A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of |
| 7366999 |
Method, system and program product providing a configuration specification language supporting a |
April 29, 2008 |
| A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at |
| 7366851 |
Processor, method, and data processing system employing a variable store gather window |
April 29, 2008 |
| A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a |
| 7360067 |
Method and data processing system for microprocessor communication in a cluster-based multi-proc |
April 15, 2008 |
| A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each process |
| 7360041 |
Method for priority scheduling and priority dispatching of store conditional operations in a sto |
April 15, 2008 |
| A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit |
| 7360021 |
System and method for completing updates to entire cache lines with address-only bus operations |
April 15, 2008 |
| A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable |
| 7359932 |
Method and data processing system for microprocessor communication in a cluster-based multi-proc |
April 15, 2008 |
| A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector withi |
| 7359847 |
Tracking converage results in a batch simulation farm network |
April 15, 2008 |
| A method and system for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation model is received |
| 7356568 |
Method, processing unit and data processing system for microprocessor communication in a multi-p |
April 8, 2008 |
| A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has ex |
| 7337280 |
Data processing system and method for efficient L3 cache directory management |
February 26, 2008 |
| A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the |
| 7305523 |
Cache memory direct intervention |
December 4, 2007 |
| A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct interventi |
| 7284102 |
System and method of re-ordering store operations within a processor |
October 16, 2007 |
| A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the ne |
| 7266489 |
Method, system and program product for determining a configuration of a digital design by refere |
September 4, 2007 |
| A method for determining the configuration of a digital design first obtains a set of latch values of a plurality of latches within the digital design. A setting of a Dial instance is then determined based upon the set of latch values by reference to a configuration database that spe |
| 7249330 |
Method, system and program product providing a configuration specification language having split |
July 24, 2007 |
| Methods, data processing systems, and program products supporting multi-cycle simulation are disclosed. According to one method, a configuration database including at least one data structure representing an instance of a Dial entity is received. The instance of the Dial entity has a |
| 7239993 |
Method, system and program product that automatically generate coverage instrumentation for conf |
July 3, 2007 |
| A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition |
| 7237070 |
Cache memory, processing unit, data processing system and method for assuming a selected invalid |
June 26, 2007 |
| At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache memories respectively affiliated with second and third processor cores. The exclusive |
| 7236918 |
Method and system for selective compilation of instrumentation entities into a simulation model |
June 26, 2007 |
| In a method of compiling a simulation model of a digital design, a compiler receives an indication of a desired set of instrumentation entities to be included within a simulation model of a digital design described by a plurality of hierarchically arranged design entities. The instru |
| 7228385 |
Processor, data processing system and method for synchronizing access to data in shared memory |
June 5, 2007 |
| A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store |
| 7213248 |
High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing |
May 1, 2007 |
| A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire |
| 7213225 |
Method, system and program product for specifying and using register entities to configure a sim |
May 1, 2007 |
| In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. W |
| 7206732 |
C-API instrumentation for HDL models |
April 17, 2007 |
| A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein |
| 7203633 |
Method and system for selectively storing and retrieving simulation data utilizing keywords |
April 10, 2007 |
| Disclosed herein is a method of storing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, result data obtained by simulation of at least one HDL model are received. In association with the result d |
| 7200717 |
Processor, data processing system and method for synchronizing access to data in shared memory |
April 3, 2007 |
| A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the ins |
| 7197604 |
Processor, data processing system and method for synchronzing access to data in shared memory |
March 27, 2007 |
| A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction e |
| 7194400 |
Method and system for reducing storage and transmission requirements for simulation results |
March 20, 2007 |
| A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for cou |
| 7168061 |
Method, system and program product for implementing a read-only dial in a configuration database |
January 23, 2007 |
| In at least one hardware definition language (HDL) file, a design entity containing a functional portion of a digital system is specified. The design entity logically contains a plurality of configuration latches each having multiple different possible latch values. The latch values of |
