| Patent Number |
Title Of Patent |
Date Issued |
| 7610500 |
Link power saving state |
October 27, 2009 |
| Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low p |
| 7360103 |
P-state feedback to operating system with hardware coordination |
April 15, 2008 |
| A mechanism for P-state feedback to operating system (OS) with hardware coordination is described herein. In one embodiment, an example of a process includes, but is not limited to, receiving data from a processor representing an average performance over a previous period of time, and |
| 7315952 |
Power state coordination between devices sharing power-managed resources |
January 1, 2008 |
| Methods and apparatuses for coordination of power state management in and electronic system. |
| 7313712 |
Link power saving state |
December 25, 2007 |
| Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low p |
| 7272741 |
Hardware coordination of power management activities |
September 18, 2007 |
| Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary |
| 6944084 |
Memory system that measures power consumption |
September 13, 2005 |
| A memory system includes a memory controller and a plurality of memory devices located on a power plane and coupled to the memory controller. The memory system further includes a sense resistor coupled to the power plane and a power source coupled to the sense resistor. The memory system |
| 6842831 |
Low latency buffer control system and method |
January 11, 2005 |
| A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated |
| 6799241 |
Method for dynamically adjusting a memory page closing policy |
September 28, 2004 |
| A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks |
| 6687172 |
Individual memory page activity timing method and system |
February 3, 2004 |
| A per bank closure system for use in a multi-bank memory includes a timer, an activity and a closure and closure register. The timer is used to define timing windows. The banks of the memory are mapped to bits in the activity and closure registers. Page activity occurring a timing window |
| 6330639 |
Method and apparatus for dynamically changing the sizes of pools that control the power consumpt |
December 11, 2001 |
| The present invention provides a method, apparatus, and system for dynamically changing the sizes of power-control pools that are used to control the power consumption levels of memory devices. In one embodiment, a request to change the sizes of the memory power-control pools is rece |
