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Inventor:
Wiedmann; Siegfried K.
Address:
Stuttgart, DE
No. of patents:
16
Patents:












Patent Number Title Of Patent Date Issued
5467311 Circuit for increasing data-valid time which incorporates a parallel latch November 14, 1995
This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by
5121357 Static random access split-emitter memory cell selection arrangement using bit line precharge June 9, 1992
This invention relates generally to the static, random access, semiconductor memory arrays which incorporate split-emitter memory cells. The latter are accessed during a read cycle of a selected memory cell by precharging all the bit lines of unselected memory cells associated with t
4992981 Double-ended memory cell array using interleaved bit lines and method of fabrication therefore February 12, 1991
The memory cell array is one in which the bit lines associated with each column of double-ended memory cells are interleaved with the bit lines of adjacent columns of memory cells. Because the spacing of metallic bit lines is governed by certain ground rules, cell length in the x-dimensi
4694433 Semiconductor memory having subarrays and partial word lines September 15, 1987
A memory structure for very large memory arrays on a chip is described where the memory array is divided into a number of subarrays. The subarrays are controlled via common word decoders and subarray decoders. The word lines of the individual subarrays are individually selectable thr
4626710 Low power logic circuit with storage charge control for fast switching December 2, 1986
A bipolar logic circuit with superior speed/power characteristics is described. Circuit operation is based on a unique dynamic minority carrier charge exchange mechanism between the input diodes performing the logic and the oppositely poled level shift diode(s) at the input of the tr
4596000 Semiconductor memory June 17, 1986
A semiconductor memory is described, whose word lines are divided into several partial word lines or partitions, wherein each partial word line is connected to a word switch and all word switches of a word line are selected and controlled via a first word control line and a second word
4535425 Highly integrated, high-speed memory with bipolar transistors August 13, 1985
A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results
4521873 Method of and circuit arrangement for reading an integrated semiconductor store with storage cel June 4, 1985
A method of and a circuit arrangement for reading an integrated MTL(I.sup.2 L) store are described, wherein prior to or during a read operation, line capacities are discharged and in addition to the word line drivers and the bit line drivers, a read/write circuit is provided. Simultaneou
4458162 TTL Logic gate July 3, 1984
A Transistor-Transistor Logic (TTL) gate is disclosed wherein a different amount of base current is applied to the inverter transistor than is applied to the base of the output transistor. In one embodiment, a current mirror circuit controls the amount of base current flowing between the
4412312 Multiaddressable highly integrated semiconductor storage October 25, 1983
A multiaddressable highly integrated semiconductor storage is provided, the storage locations of which are addressable by several independent address systems for parallel reading and/or writing. The storage locations are each made up of n storage elements. One storage location consists,
4346458 I.sup.2 L Monolithically integrated storage arrangement August 24, 1982
Monolithically integrated storage arrangement with storage cells arranged in a matrix and consisting of two cross-coupled I.sup.2 L structures (T1, T2 and T1', T2') each in the manner of a flip-flop, wherein the read signal is derived from the charge carrier current reinjected into the
4334294 Restore circuit for a semiconductor storage June 8, 1982
Disclosed is a restore circuit for restoring an integrated semiconductor storage array having storage cells consisting of bipolar transistors. The restore circuit includes a reference voltage generator, an impedance converter, and switches to connect the reference voltage generator and t
4319344 Method and circuit arrangement for discharging bit line capacitances of an integrated semiconduc March 9, 1982
A method and arrangement is provided for selecting and discharging a pair of bit lines of a plurality of charged pairs of bit lines of a memory circuit having cells of the merged transistor logic type. A selected pair of bit lines is discharged through a selected cell coupled to the sele
4313177 Storage cell simulation for generating a reference voltage for semiconductor stores in mtl techn January 26, 1982
Disclosed is a simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology. The simulated storage cell structure includes n elongated regions of P-type diffusion arranged in parallel to each oth
4280198 Method and circuit arrangement for controlling an integrated semiconductor memory July 21, 1981
In integrated semiconductor memory cell arrangements, particularly integrated semiconductor memory cell arrangements using merged transistor logic configurations, line capacitances are discharged before accessing to reduce access time and power consumption. Individual bit line transistor
4254428 Self-aligned Schottky diode structure and method of fabrication March 3, 1981
A Schottky diode structure and self-aligned fabrication method wherein the cathode or ohmic contact is disposed in the center of the anode or Schottky contact and is isolated therefrom by an overlapping layer of insulation. This structure has a reduced area size; it allows the use of










 
 
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