| Patent Number |
Title Of Patent |
Date Issued |
| 7045070 |
Method of producing an electrode configuration and method of electrically contacting the electro |
May 16, 2006 |
| The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at least slightly etchable by dry etching. The mask contains a metal silicide, a metal nitride or a metal oxide. |
| 6887437 |
Reactor configuration and method for producing it |
May 3, 2005 |
| A reactor configuration contains a housing connected to a silicon wafer. The silicon wafer has pores extending from a first main area of the silicon wafer into an interior of the silicon wafer, preferably as far as a second main area of the silicon wafer. A catalyst layer at least partly |
| 6710388 |
Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the |
March 23, 2004 |
| A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric lay |
| 6670668 |
Microelectronic structure, method for fabricating it and its use in a memory cell |
December 30, 2003 |
| A microelectronic structure that is suitable, in particular, as part of a storage capacitor includes a semiconductor structure, a barrier structure, an electrode structure, and a dielectric structure made of a high-epsilon material. The electrode structure has a tensile mechanical layer |
| 6656376 |
Process for cleaning CVD units |
December 2, 2003 |
| A cleaning process for cleaning CVD units is disclosed. In the cleaning process, alkaline earth metal and/or metal-containing process residues, which form an amorphous film on reactor walls, are removed using a dry etching medium containing free diketones at a greatly reduced pressure an |
| 6614575 |
Optical structure and method for producing the same |
September 2, 2003 |
| An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating |
| 6573542 |
Capacitor electrodes arrangement with oxygen iridium between silicon and oxygen barrier layer |
June 3, 2003 |
| The invention relates to a microelectronic structure. In the structure, an oxygen-containing iridium layer is embedded between a silicon-containing layer and an oxygen barrier layer. The iridium layer is especially produced by a sputter process in an oxygen atmosphere with a low oxygen |
| 6558770 |
Perforated work piece, and method for producing it |
May 6, 2003 |
| A substrate made from silicon has a first region and a second region. Through pores are formed in the first region. Pores that do not traverse the substrate are provided in the second region. The production of the work piece is performed with the aid of electrochemical etching of the |
| 6552385 |
DRAM memory capacitor having three-layer dielectric, and method for its production |
April 22, 2003 |
| A DRAM capacitor is described that contains a BaSrTiO.sub.3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped. |
| 6548846 |
Storage capacitor for a DRAM |
April 15, 2003 |
| A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is |
| 6495415 |
Method for fabricating a patterned layer |
December 17, 2002 |
| A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at least one migration region; applying a layer material; adding a material to the layer material; and performing a heat treatment |
| 6468348 |
Method of producing an open form |
October 22, 2002 |
| An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is |
| 6458603 |
Method of fabricating a micro-technical structure, and micro-technical component |
October 1, 2002 |
| The invention relates to a method for fabricating in particular a TMR element for use in a MRAM, wherein a mask is arranged on a substrate and structured in such a manner that it shadows but does not cover a surface region of the substrate, and wherein material of the structure which is |
| 6215140 |
Electrically programmable non-volatile memory cell configuration |
April 10, 2001 |
| A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls o |
| 6204119 |
Manufacturing method for a capacitor in an integrated memory circuit |
March 20, 2001 |
| A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material |
| 6194765 |
Integrated electrical circuit having at least one memory cell and method for fabricating it |
February 27, 2001 |
| An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two |
| 6190991 |
Method for fabricating a capacitor |
February 20, 2001 |
| A method for fabricating a capacitor includes the formation of a self-aligned and essentially amorphous passivation edge web. The passivation edge web is formed in the course of a BST vapor phase deposition after prior etching of the lower metal electrode and of the barrier layer, th |
| 6165835 |
Method for producing a silicon capacitor |
December 26, 2000 |
| In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole s |
| 6140177 |
Process of forming a semiconductor capacitor including forming a hemispherical grain statistical |
October 31, 2000 |
| For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective |
| 6133126 |
Method for fabricating a dopant region |
October 17, 2000 |
| A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulatin |
| 6127220 |
Manufacturing method for a capacitor in an integrated storage circuit |
October 3, 2000 |
| On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so th |
| 6117790 |
Method for fabricating a capacitor for a semiconductor memory configuration |
September 12, 2000 |
| A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive laye |
| 6040995 |
Method of operating a storage cell arrangement |
March 21, 2000 |
| For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide laye |
| 6022786 |
Method for manufacturing a capacitor for a semiconductor arrangement |
February 8, 2000 |
| For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the |
| 5964652 |
Apparatus for the chemical-mechanical polishing of wafers |
October 12, 1999 |
| An apparatus for the chemical-mechanical polishing of wafers has a rotating disk provided with a polishing body, a supply device for a polishing fluid and a holding device for the wafer. An axis of the disk runs parallel to the surface of the wafer. A cylindrical edge surface of the disk |
| 5866452 |
Process for producing a silicon capacitor |
February 2, 1999 |
| To produce a silicon capacitor, hole apertures at whose surface a conductive zone (40) is formed by doping and whose surface is provided with a dielectric layer (6) and a conductive layer (7) are generated in an n-doped silicon substrate (1). To compensate for mechanical strains in the |
| 5817553 |
Process for manufacturing capacitors in a solid state configuration |
October 6, 1998 |
| Capacitors, in particular stacked capacitors for a dynamic memory cell configuration are manufactured by first forming a sequence of layers, which include layers made of a first conductive material alternating with layers made of a second material. The second material can be selectively |
| 5500385 |
Method for manufacturing a silicon capacitor by thinning |
March 19, 1996 |
| For manufacturing a silicon capacitor, hole openings are produced in an n-doped silicon substrate, a p.sup.+ -doped region is formed at the surface thereof and this surface is provided with a dielectric layer together with a conductive layer. The silicon substrate is thinned with an |
| 5347696 |
Method for manufacturing a multi-layer capacitor |
September 20, 1994 |
| For manufacturing a multi-layer capacitor, a layer structure (2, 3, 4) is applied onto a substrate (1), said layer structure comprising conductive layers (2, 4) and dielectric layers (3) in alternation and successive conductive layers (2, 4) therein being respectively formed of one of tw |
