| Patent Number |
Title Of Patent |
Date Issued |
| 7454675 |
Testing of a programmable device |
November 18, 2008 |
| A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequent |
| 7219314 |
Application-specific methods for testing molectronic or nanoscale devices |
May 15, 2007 |
| Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of "nanotechnology" and molecular-scale technology, or "molectronics." Test methods identify alternativ |
| 7127697 |
Methods of utilizing programmable logic devices having localized defects in application-specific |
October 24, 2006 |
| Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no e |
| 7007250 |
Application-specific methods useful for testing look up tables in programmable logic devices |
February 28, 2006 |
| Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be |
| 6920621 |
Methods of testing for shorts in programmable logic devices using relative quiescent current mea |
July 19, 2005 |
| Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused |
| 6891395 |
Application-specific testing methods for programmable logic devices |
May 10, 2005 |
| Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuit |
| 6817006 |
Application-specific testing methods for programmable logic devices |
November 9, 2004 |
| Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuit |
| 6664808 |
Method of using partially defective programmable logic devices |
December 16, 2003 |
| FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can ex |
| 6651238 |
Providing fault coverage of interconnect in an FPGA |
November 18, 2003 |
| Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. |
| 6611477 |
Built-in self test using pulse generators |
August 26, 2003 |
| A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that i |
| 6594797 |
Methods and circuits for precise edge placement of test signals |
July 15, 2003 |
| Described are methods and circuits for accurately placing signal transitions, or "edges," simultaneously on two or more pins of an integrated circuit (IC). A conventional tester is connected to an integrated circuit, such as a programmable logic device. The integrated circuit is adap |
| 6594610 |
Fault emulation testing of programmable logic devices |
July 15, 2003 |
| A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The config |
| 6539508 |
Methods and circuits for testing programmable logic |
March 25, 2003 |
| Described is a test circuit that can be instantiated on a programmable logic device to perform at-speed functional tests of programmable resources, including internal memory and routing resources. The resources to be tested are configured to instantiate a counter circuit connected to |
| 6466520 |
Built-in AC self test using pulse generators |
October 15, 2002 |
| A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that i |
| 6356514 |
Built-in self test method for measuring clock to out delays |
March 12, 2002 |
| A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that i |
| 6324672 |
Method for configuring circuits over a data communications link |
November 27, 2001 |
| A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit- |
| 6233205 |
Built-in self test method for measuring clock to out delays |
May 15, 2001 |
| A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that i |
| 6232845 |
Circuit for measuring signal delays in synchronous memory elements |
May 15, 2001 |
| A circuit measures a signal propagation delay through a series of memory elements. In one embodiment the memory elements are configured in series so that together they form a delay circuit. In another embodiment the memory elements are configured in a loop to form a ring oscillator. Each |
| 6219305 |
Method and system for measuring signal propagation delays using ring oscillators |
April 17, 2001 |
| A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal |
| 6075418 |
System with downstream set or clear for measuring signal propagation delays on integrated circui |
June 13, 2000 |
| A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous |
| 6069849 |
Method and system for measuring signal propagation delays using the duty cycle of a ring oscilla |
May 30, 2000 |
| A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that inclu |
| 6023565 |
Method for configuring circuits over a data communications link |
February 8, 2000 |
| A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit- |
| 5673198 |
Concurrent electronic circuit design and implementation |
September 30, 1997 |
| A system for providing real time design feedback to a user of a data processing system for designing an electronic circuit includes a display system, a graphical, textual or mixed user input process which displays user input on the display system for designing an electronic circuit, and |
