| Patent Number |
Title Of Patent |
Date Issued |
| 7254634 |
Managing web tier session state objects in a content delivery network (CDN) |
August 7, 2007 |
| Business applications running on a content delivery network (CDN) having a distributed application framework can create, access and modify state for each client. Over time, a single client may desire to access a given application on different CDN edge servers within the same region and e |
| 7127713 |
Java application framework for use in a content delivery network (CDN) |
October 24, 2006 |
| An application deployment model for enterprise applications to enable such applications to be deployed to and executed from a globally distributed computing platform, such as an Internet content delivery network (CDN). According to the invention, application developers separate their Web |
| 7111057 |
Method and system for purging content from a content delivery network |
September 19, 2006 |
| A content file purge mechanism for a content delivery network (CDN) is described. A Web-enabled portal is used by CDN customers to enter purge requests securely. A purge request identifies one or more content files to be purged. The purge request is pushed over a secure link from the |
| 6549930 |
Method for scheduling threads in a multithreaded processor |
April 15, 2003 |
| A method is provided for scheduling execution of a plurality of threads executed in a multithreaded processor. Resource utilizations of each of the plurality of threads are measured while the plurality of threads are concurrently executing in the multithreaded processor. Each of the |
| 6374367 |
Apparatus and method for monitoring a computer system to guide optimization |
April 16, 2002 |
| A method for sampling the performance of a computer system is provided. The computer system includes a plurality of functional units. The method selects transactions to be processed by a particular functional unit of the computer system. State information is stored while the selected |
| 6332178 |
Method for estimating statistics of properties of memory system transactions |
December 18, 2001 |
| A method estimates statistics of properties of transactions processed by a memory sub-system of a computer system. The method randomly selects memory transactions processed by the memory sub-system. States of the system are recorded as samples while the selected transaction are processed |
| 6237073 |
Method for providing virtual memory to physical memory page mapping in a computer operating syst |
May 22, 2001 |
| A method is provided for guiding virtual-to-physical mapping policies in a computer system including a processor and a memory. State information is randomly sampled from selected memory references in a stream of memory references issued by the processor to the memory. Cache hit/miss stat |
| 6202127 |
Apparatus for spatial and temporal sampling in a computer memory system |
March 13, 2001 |
| An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. T |
| 6195748 |
Apparatus for sampling instruction execution information in a processor pipeline |
February 27, 2001 |
| An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. E |
| 6175814 |
Apparatus for determining the instantaneous average number of instructions processed |
January 16, 2001 |
| An apparatus is provided for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock. The number of instructions entering a particular stage of the pipeline are stored in a queue during each of |
| 6163840 |
Method and apparatus for sampling multiple potentially concurrent instructions in a processor pi |
December 19, 2000 |
| An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A |
| 6148396 |
Apparatus for sampling path history in a processor pipeline |
November 14, 2000 |
| An apparatus is provided for collecting state information associated with an execution path of recently processed instructions in a processor pipeline of a computer system. The apparatus identifies a class of instructions to be sampled. Path-identifying state information of a current |
| 6119075 |
Method for estimating statistics of properties of interactions processed by a processor pipeline |
September 12, 2000 |
| Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A set of instructions are r |
| 6112317 |
Processor performance counter for sampling the execution frequency of individual instructions |
August 29, 2000 |
| A processor includes an execution pipeline and a retire unit coupled to an end of the execution pipeline. The processor executes instructions of a program. An apparatus for collecting performance data while the instructions are executing includes a register coupled to the retire unit |
| 6092180 |
Method for measuring latencies by randomly selected sampling of the instructions while the instr |
July 18, 2000 |
| In a method for scheduling instructions executed in a computer system including a processor and a memory subsystem, pipeline latencies and resource utilization are measured by sampling hardware while the instructions are executing. The instructions are then scheduled according to the |
| 6070009 |
Method for estimating execution rates of program execution paths |
May 30, 2000 |
| A method is provided for estimating execution rates of program executions paths. The method samples path-identifying state information of selected instructions while executing the program in a processor. A control flow graph of the program is supplied, the control flow graph includes a |
| 6000044 |
Apparatus for randomly sampling instructions in a processor pipeline |
December 7, 1999 |
| An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are iden |
| 5964867 |
Method for inserting memory prefetch operations based on measured latencies in a program optimiz |
October 12, 1999 |
| A method is provided for optimizing a program by inserting memory prefetch operations in the program executing in a computer system. The computer system includes a processor and a memory. Latencies of instructions of the program are measured by hardware while the instructions are process |
| 5923872 |
Apparatus for sampling instruction operand or result values in a processor pipeline |
July 13, 1999 |
| An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a par |
| 5809450 |
Method for estimating statistics of properties of instructions processed by a processor pipeline |
September 15, 1998 |
| A method is provided for estimating statistics of properties of instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Some of the fetched instructions are randomly |
| 5796939 |
High frequency sampling of processor performance counters |
August 18, 1998 |
| In a computer system, an apparatus is configured to collect performance data of a computer system including a plurality of processors for concurrently executing instructions of a program. A plurality of performance counters are coupled to each processor. The performance counters stor |
