| |
 |
|
|
Inventor: Weatherford; James R.
Address: Lake Dallas, TX
No. of patents: 7
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 4942518 |
Cache store bypass for computer |
July 17, 1990 |
| A physical cache unit (100) is used within a computer (20). The computer (20) further includes a main memory (99) a memory control unit (22), inputs/output processors (54, 68) and a central processor (156). The central processor includes an address translation unit (118), an instruct |
| 4926317 |
Hierarchical memory system with logical cache, physical cache, and address translation unit for |
May 15, 1990 |
| A vector processing computer (20) includes a memory control unit (22), main memory (99), a central processor (156), a service processing unit (42) and a plurality of input/output processors (54, 68). The central processor (156) includes a physical cache unit (100), an address translation |
| 4884191 |
Memory array unit for computer |
November 28, 1989 |
| The computer (10) includes a memory control unit (12), a central processing unit (14) and a memory array unit (16). A plurality of memory array planes (36, 38, 40 and 42) are included within the memory array unit (16). A latch (82) receives write data from the memory control unit (12) th |
| 4760522 |
Intermixing of different capacity memory array units in a computer |
July 26, 1988 |
| A memory array unit (20) is used within a main memory (26) of a computer system (10). The memory (26) comprises a plurality of memory array units (20, 22, 24) and each of the memory array units (20, 22, 24) has an allocated address range of 0 to 16 megabytes. However, the memory array |
| 4663728 |
Read/modify/write circuit for computer memory operation |
May 5, 1987 |
| A read/modify/write circuit (10) for a computer is used in conjunction with a main memory (12) in which block operations are executed using a plurality of data units. The circuit (10) includes a first register connected to receive a data block from the main memory (12), a second regi |
| 4646233 |
Physical cache unit for computer |
February 24, 1987 |
| A physical cache unit (100) is used within a computer (20). The computer (20) further includes a main memory (99) a memory control unit (22), inputs/output processors (54, 68) and a central processor (156). The central processor includes an address translation unit (118), an instruct |
| 4620275 |
Computer system |
October 28, 1986 |
| A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main |
|
|
|
