| Patent Number |
Title Of Patent |
Date Issued |
| 7565343 |
Search apparatus and search management method for fixed-length data |
July 21, 2009 |
| Fixed-length data (560) contained in a database (560) are segmented into a number of pieces of data that are searchable at a time and searching is performed at high speed. As means for it, a pointer table (500), a secondary pointer table, a local table, and a fixed-length-data table are |
| 7469243 |
Method and device for searching fixed length data |
December 23, 2008 |
| Embodiments of the present invention provide method and device for searching fixed length data. The device includes a hash operation means for operating and outputting a hash value of inputted fixed length data, a data table memory consisting of N numbers of memory banks, where N is |
| 7460538 |
Communication control apparatus and method for searching an internet protocol address |
December 2, 2008 |
| A communication control apparatus includes search information associated with a tree structure. A mask prefix is associated with at least one entry, each entry including information on the mask length of a mask prefix associated therewith and a sort key. Each entry is assigned to a n |
| 7124278 |
Information processing device and method, program, data structure, and computer-readable recordi |
October 17, 2006 |
| Upon implementing a data registration into or a data retrieval from a data table (3) where first item data are registered along with corresponding second item data, there are used a first pointer table (1) where pointers to part of the registered data in the data table are registered in |
| 7093067 |
DRAM architecture enabling refresh and access operations in the same bank |
August 15, 2006 |
| To provide a DRAM that reduces access latency during refresh and performs refresh for any non-accessed bank in parallel with normal memory accesses. Furthermore, the DRAM allows access to a bank that is undergoing refresh. The DRAM includes a circuit for directing refresh execution b |
| 7061818 |
Memory and refresh method for memory |
June 13, 2006 |
| The present invention discloses a memory, and a refresh method for memory, which performs a normal access and refresh one after another within one operation cycle of SRAM. The memory of the present invention comprises a refresh enable which directs execution of refresh, a row address cou |
| 6977857 |
DRAM and refresh method thereof |
December 20, 2005 |
| The present invention relates to a DRAM having a memory array that is divided into a plurality of memory blocks. A memory block having a long data retention time is selected from the plurality of memory blocks and a logical address is allocated to the selected memory block. The selected |
| 6961802 |
Data input/output device, memory system, data input/output circuit, and data input/output method |
November 1, 2005 |
| When an output of data is switched from a memory to a memory controller, the memory controller takes in write data output from the memory, and outputs the write data taken in to a data bus. Subsequently, the memory controller outputs read data taken thereinto to the data bus, and then |
| 6925028 |
DRAM with multiple virtual bank architecture for random row access |
August 2, 2005 |
| A DRAM and access method for DRAM with a high data rate in a random row access mode. The DRAM includes a plurality of memory blocks composed of a plurality of storage segments each with a series of main word lines and sub-word lines. Each memory block is decoded into multiple segments an |
| 6898661 |
Search memory, memory search controller, and memory search method |
May 24, 2005 |
| A distributor and a search controller are added to the memory. A search is performed with an algorithm such as quick search by repeating reading of memory cells, comparing of the reading result, and narrowing down of entries to be compared based on the comparison result. Performing this |
| 6650573 |
Data input/output method |
November 18, 2003 |
| The present invention discloses a method for data input/output for memory which minimizes losses of data interruption when switching between reading and writing. A method for data input/output comprises the steps of: holding predetermined data from memory array 12 upon m-th (m is integer |
| 6545932 |
SDRAM and method for data accesses of SDRAM |
April 8, 2003 |
| An SRAM which eliminates any seam in consecutive read/write data flows when the burst-length is short, thus making it possible to achieve a seamless access in the burst-mode against data of different row-addresses between banks. This operation enables the band-width of SDRAM to approxima |
| 6252794 |
DRAM and data access method for DRAM |
June 26, 2001 |
| A DRAM includes a plurality of DRAM cells; sense amplifiers respectively corresponding to the plural DRAM cells; and means for activating merely a sense amplifier corresponding to a cell to be accessed among the plural DRAM cells, so that merely sense amplifiers in a number corresponding |
| 6085300 |
DRAM system with simultaneous burst read and write |
July 4, 2000 |
| A DRAM system is described that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order. As a result, provided is a memory system constituted by DRAM whereby a seamless operation is assured not only for |
| 5553252 |
Device for controlling data transfer between chips via a bus |
September 3, 1996 |
| A draw control chip and video chips V1-V4 are provided. They are connected by a 64-bit data bus, a 4-bit program signal line, and a 1-bit ready signal line. The video chip V1 comprises a decoder DEC1, a program buffer address register PBAR, a sequencer SEQ, a program buffer PB, a decoder |
| 4845477 |
Color blinking system |
July 4, 1989 |
| An apparatus and method for color blinking in a color display system. The system of this invention comprises: a palette means for converting color codes from a processor to color video signals for ultimate display in a color display, blink color registers for storing a first color video |
