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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ward, III; John Wesley
Address:
Pflugerville, TX
No. of patents:
9
Patents:












Patent Number Title Of Patent Date Issued
8145885 Apparatus for randomizing instruction thread interleaving in a multi-thread processor March 27, 2012
A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread
7827388 Apparatus for adjusting instruction thread priority in a multi-thread processor November 2, 2010
Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads
7487334 Branch encoding before instruction cache write February 3, 2009
Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch p
7475223 Fetch-side instruction dispatch group formation January 6, 2009
An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions pr
7401208 Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor July 15, 2008
A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread
7401207 Apparatus and method for adjusting instruction thread priority in a multi-thread processor July 15, 2008
Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads
7360062 Method and apparatus for selecting an instruction thread for processing in a multi-thread proces April 15, 2008
The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement co
7305586 Accessing and manipulating microprocessor state December 4, 2007
A microprocessor includes an externally accessible port and a serial communication bus connected to the port. An execution pipeline of the processor includes a pipeline satellite circuit coupling the pipeline to the bus. The satellite enables an external agent to provide an instructi
7269715 Instruction grouping history on fetch-side dispatch group formation September 11, 2007
An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions










 
 
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