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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Wang; Ying-Lang
Address:
Hsin-Chu, TW
No. of patents:
10
Patents:












Patent Number Title Of Patent Date Issued
7528478 Semiconductor devices having post passivation interconnections and a buffer layer May 5, 2009
An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pat
7199045 Metal-filled openings for submicron devices and methods of manufacture thereof April 3, 2007
A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the
7128821 Electropolishing method for removing particles from wafer surface October 31, 2006
An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and
7071100 Method of forming barrier layer with reduced resistivity and improved reliability in copper dama July 4, 2006
A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene
7026233 Method for reducing defects in post passivation interconnect process April 11, 2006
A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer
6985222 Chamber leakage detection by measurement of reflectivity of oxidized thin film January 10, 2006
A system and method for detecting chamber leakage by measuring the reflectivity of an oxidized thin film. In a preferred embodiment, a method of detecting leaks in a chamber includes providing a first monitor workpiece, placing the first monitor workpiece in the chamber, and forming
6903011 Displacement method to grow cu overburden June 7, 2005
A damascene-formed conductive region having a recess formed at the top surface thereof by a chemical-mechanical polish (CMP) process is repaired or regrown using a displacement method. A displacement material is deposited over the recessed conductive material. The displacement material
6815072 Method to solve particle performance of FSG layer by using UFU season film for FSG process November 9, 2004
A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the
6479098 Method to solve particle performance of FSG layer by using UFU season film for FSG process November 12, 2002
A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the
6399522 PE-silane oxide particle performance improvement June 4, 2002
A method of forming a PE-silane oxide layer with a greatly reduced particle count is described. A semiconductor substrate is provided over which a silicon oxide film is to be formed. The silicon oxide film is formed by the steps of: 1) pre-flowing a non-silane gas into a deposition chamb










 
 
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