| Patent Number |
Title Of Patent |
Date Issued |
| 7169706 |
Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper depositio |
January 30, 2007 |
| An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor |
| 6992004 |
Implanted barrier layer to improve line reliability and method of forming same |
January 31, 2006 |
| A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided |
| 6979903 |
Integrated circuit with dielectric diffusion barrier layer formed between interconnects and inte |
December 27, 2005 |
| An integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier |
| 6939803 |
Method for forming conductor reservoir volume for integrated circuit interconnects |
September 6, 2005 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein incl |
| 6893955 |
Manufacturing seedless barrier layers in integrated circuits |
May 17, 2005 |
| An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barri |
| 6861349 |
Method of forming an adhesion layer with an element reactive with a barrier layer |
March 1, 2005 |
| A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a |
| 6841473 |
Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap |
January 11, 2005 |
| A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier l |
| 6815340 |
Method of forming an electroless nucleation layer on a via bottom |
November 9, 2004 |
| A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and formin |
| 6710452 |
Coherent diffusion barriers for integrated circuit interconnects |
March 23, 2004 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a bar |
| 6674170 |
Barrier metal oxide interconnect cap in integrated circuits |
January 6, 2004 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A ba |
| 6663787 |
Use of ta/tan for preventing copper contamination of low-k dielectric layers |
December 16, 2003 |
| A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier |
| 6657303 |
Integrated circuit with low solubility metal-conductor interconnect cap |
December 2, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A ba |
| 6656836 |
Method of performing a two stage anneal in the formation of an alloy interconnect |
December 2, 2003 |
| A method of performing a two stage anneal in the formation of an alloy interconnect can include forming a via aperture in a dielectric layer where the via aperture provides an area for formation of a via, providing a seed layer along lateral side walls of the via aperture, rapid thermal |
| 6649034 |
Electro-chemical metal alloying for semiconductor manufacturing |
November 18, 2003 |
| The present invention provides an alloy electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A p |
| 6642145 |
Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed b |
November 4, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable |
| 6621290 |
Characterization of barrier layers in integrated circuit interconnects |
September 16, 2003 |
| A test structure and method for testing a semiconductor material is provided with a semiconductor wafer having an electrical ground and a source of electrical potential. A conductor layer is placed over the semiconductor wafer and a semiconductor material is placed over the conductor |
| 6617176 |
METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORM |
September 9, 2003 |
| A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or |
| 6590288 |
Selective deposition in integrated circuit interconnects |
July 8, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first conductor core is connected to the semiconductor device. A low dielectric constant dielectric layer is formed over the semiconductor substrate and has |
| 6589408 |
Non-planar copper alloy target for plasma vapor deposition systems |
July 8, 2003 |
| A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a |
| 6566248 |
Graphoepitaxial conductor cores in integrated circuit interconnects |
May 20, 2003 |
| A manufacturing method is provided for an integrated circuit having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrie |
| 6555909 |
Seedless barrier layers in integrated circuits and a method of manufacture therefor |
April 29, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein |
| 6548395 |
Method of promoting void free copper interconnects |
April 15, 2003 |
| Cu or a Cu alloy is deposited to partially fill openings in a dielectric layer and then annealed. Incomplete filling leaves room in the openings to accommodate a volume change associated with grain growth and, hence, prevents the generation of voids. The openings are then completely fill |
| 6541860 |
Barrier-to-seed layer alloying in integrated circuit interconnects |
April 1, 2003 |
| An integrated circuit and a method for manufacture thereof are provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. An opening is formed in the dielectric layer. A barrier layer with an alloying element |
| 6534865 |
Method of enhanced fill of vias and trenches |
March 18, 2003 |
| A manufacturing method and apparatus for filling vias and trenches in integrated circuits is provided having a substrate with a device provided thereon. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a |
| 6531780 |
Via formation in integrated circuit interconnects |
March 11, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a first conductor core. A via dielect |
| 6525425 |
Copper interconnects with improved electromigration resistance and low resistivity |
February 25, 2003 |
| Copper interconnects are formed by depositing substantially pure copper into the lower portion of an interconnect opening. The upper portion of the interconnect opening is then filled with doped copper followed by a planarization process. The resulting copper interconnect exhibits reduce |
| 6518185 |
Integration scheme for non-feature-size dependent cu-alloy introduction |
February 11, 2003 |
| In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the |
| 6518167 |
Method of forming a metal or metal nitride interface layer between silicon nitride and copper |
February 11, 2003 |
| A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic |
| 6472757 |
Conductor reservoir volume for integrated circuit interconnects |
October 29, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein incl |
| 6469385 |
Integrated circuit with dielectric diffusion barrier layer formed between interconnects and inte |
October 22, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable |
| 6462417 |
Coherent alloy diffusion barrier for integrated circuit interconnects |
October 8, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, an al |
| 6462416 |
Gradated barrier layer in integrated circuit interconnects |
October 8, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening formed therein is formed on the semiconductor substrate. A barrier layer of barrier metal and barrier compound lines |
| 6455938 |
Integrated circuit interconnect shunt layer |
September 24, 2002 |
| An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the ope |
| 6445070 |
Coherent carbide diffusion barrier for integrated circuit interconnects |
September 3, 2002 |
| An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a ba |
| 6433402 |
Selective copper alloy deposition |
August 13, 2002 |
| Copper or a low resistivity copper alloy is initially deposited to fill relatively narrow openings leaving relatively wider openings unfilled. A copper alloy having improved electromigration resistance with respect to copper is then selectively deposited to fill the relatively wider |
| 6417566 |
Void eliminating seed layer and conductor core integrated circuit interconnects |
July 9, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein |
| 6417100 |
Annealing ambient in integrated circuit interconnects |
July 9, 2002 |
| A method of manufacturing an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening provided therein is formed on the semiconductor substrate. A barrier layer lines the channel opening. A conductor core f |
| 6403474 |
Controlled anneal conductors for integrated circuit interconnects |
June 11, 2002 |
| A method is provided for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is |
| 6346479 |
Method of manufacturing a semiconductor device having copper interconnects |
February 12, 2002 |
| A copper interconnect is formed by creating an opening in a dielectric layer. Copper is then deposited in a non-conformal electroplating process to fill a portion of the opening. A second electroplating process is then performed to conformally deposit copper in the remaining unfilled por |
| 6190752 |
Thin films having rock-salt-like structure deposited on amorphous surfaces |
February 20, 2001 |
| A thin film of material having a rock-salt-like structure is deposited on a smooth amorphous substrate surface by ion beam assisted deposition. |
