| Patent Number |
Title Of Patent |
Date Issued |
| 7555632 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
June 30, 2009 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 7523296 |
System and method for handling exceptions and branch mispredictions in a superscalar microproces |
April 21, 2009 |
| An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the m |
| 7516305 |
System and method for retiring approximately simultaneously a group of instructions in a supersc |
April 7, 2009 |
| An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the m |
| 7487333 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
February 3, 2009 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 7447876 |
System and method for handling load and/or store operations in a superscalar microprocessor |
November 4, 2008 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load request |
| 7343473 |
System and method for translating non-native instructions to native instructions for processing |
March 11, 2008 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a p |
| 7162610 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
January 9, 2007 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 7051187 |
Superscalar RISC instruction scheduling |
May 23, 2006 |
| A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address |
| 7028161 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
April 11, 2006 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 7000097 |
System and method for handling load and/or store operations in a superscalar microprocessor |
February 14, 2006 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load request |
| 6986024 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
January 10, 2006 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6965987 |
System and method for handling load and/or store operations in a superscalar microprocessor |
November 15, 2005 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load request |
| 6959375 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
October 25, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6957320 |
System and method for handling load and/or store operations in a superscalar microprocessor |
October 18, 2005 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load request |
| 6954847 |
System and method for translating non-native instructions to native instructions for processing |
October 11, 2005 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 6948052 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
September 20, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6941447 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
September 6, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6934829 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 23, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6920548 |
System and method for retiring approximately simultaneously a group of instructions in a supersc |
July 19, 2005 |
| An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the m |
| 6915412 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 5, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6775761 |
System and method for retiring approximately simultaneously a group of instructions in a supersc |
August 10, 2004 |
| An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the m |
| 6735685 |
System and method for handling load and/or store operations in a superscalar microprocessor |
May 11, 2004 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load request |
| 6647485 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
November 11, 2003 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6434693 |
System and method for handling load and/or store operations in a superscalar microprocessor |
August 13, 2002 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load request |
| 6412064 |
System and method for retiring approximately simultaneously a group of instructions in a supersc |
June 25, 2002 |
| An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the m |
| 6289433 |
Superscalar RISC instruction scheduling |
September 11, 2001 |
| A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address |
| 6282630 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
August 28, 2001 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 6272619 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 7, 2001 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6263423 |
System and method for translating non-native instructions to native instructions for processing |
July 17, 2001 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 6256720 |
High performance, superscalar-based computer system with out-of-order instruction execution |
July 3, 2001 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6230254 |
System and method for handling load and/or store operators in a superscalar microprocessor |
May 8, 2001 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load request |
| 6131157 |
System and method for retiring approximately simultaneously a group of instructions in a supersc |
October 10, 2000 |
| An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the m |
| 6128723 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
October 3, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6101594 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 8, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6092181 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 18, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6038654 |
High performance, superscalar-based computer system with out-of-order instruction execution |
March 14, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6038653 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
March 14, 2000 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 5987593 |
System and method for handling load and/or store operations in a superscalar microprocessor |
November 16, 1999 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load request |
| 5983334 |
Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instruc |
November 9, 1999 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 5974526 |
Superscalar RISC instruction scheduling |
October 26, 1999 |
| A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address |
| 5961629 |
High performance, superscalar-based computer system with out-of-order instruction execution |
October 5, 1999 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 5832292 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
November 3, 1998 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 5826055 |
System and method for retiring instructions in a superscalar microprocessor |
October 20, 1998 |
| An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the m |
| 5737624 |
Superscalar risc instruction scheduling |
April 7, 1998 |
| A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address |
| 5734856 |
System and method for generating supplemental ready signals to eliminate wasted cycles between o |
March 31, 1998 |
| A data processing system comprising a controller, a functional unit coupled to the controller, to perform a first operation having an operational latency, and a supplemental ready signal generator coupled to the controller. The functional unit requires an initial lead time period bef |
| 5689720 |
High-performance superscalar-based computer system with out-of-order instruction execution |
November 18, 1997 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instr |
| 5664156 |
Microcontroller with a reconfigurable program status word |
September 2, 1997 |
| A microcontroller routs bits of a PSW to and from a bus depending on a mode. Whenever in a mode compatible with a prior generation microcontroller, address and routing circuitry using decoders and multiplexers, during a read operation, places bits of the PSW of the current generation |
| 5659782 |
System and method for handling load and/or store operations in a superscalar microprocessor |
August 19, 1997 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load request |
| 5619666 |
System for translating non-native instructions to native instructions and combining them into a |
April 8, 1997 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 5560032 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
September 24, 1996 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program ins |
