| Patent Number |
Title Of Patent |
Date Issued |
| 7616499 |
Retention margin program verification |
November 10, 2009 |
| Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence an |
| 7606074 |
Word line compensation in non-volatile memory erase operations |
October 20, 2009 |
| Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select ga |
| 7512014 |
Comprehensive erase verification for non-volatile memory |
March 31, 2009 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 7508720 |
Systems for comprehensive erase verification in non-volatile memory |
March 24, 2009 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 7495956 |
Reducing read disturb for non-volatile storage |
February 24, 2009 |
| A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting o |
| 7463532 |
Comprehensive erase verification for non-volatile memory |
December 9, 2008 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 7457178 |
Trimming of analog voltages in flash memory devices |
November 25, 2008 |
| A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a select |
| 7450435 |
Systems for comprehensive erase verification in non-volatile memory |
November 11, 2008 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
| 7450433 |
Word line compensation in non-volatile memory erase operations |
November 11, 2008 |
| Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select ga |
| 7447086 |
Selective program voltage ramp rates in non-volatile memory |
November 4, 2008 |
| A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. |
| 7447065 |
Reducing read disturb for non-volatile storage |
November 4, 2008 |
| A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting o |
| 7440318 |
Reducing read disturb for non-volatile storage |
October 21, 2008 |
| A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting o |
| 7349258 |
Reducing read disturb for non-volatile storage |
March 25, 2008 |
| A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting o |
| 7295478 |
Selective application of program inhibit schemes in non-volatile memory |
November 13, 2007 |
| A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. |
| 7295473 |
System for reducing read disturb for non-volatile storage |
November 13, 2007 |
| A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the sou |
| 7262994 |
System for reducing read disturb for non-volatile storage |
August 28, 2007 |
| A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the sou |
| 7254071 |
Flash memory devices with trimmed analog voltages |
August 7, 2007 |
| A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a select |
| 7230854 |
Method for programming non-volatile memory with self-adjusting maximum program loop |
June 12, 2007 |
| The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elem |
| 7218552 |
Last-first mode and method for programming of non-volatile memory with reduced program disturb |
May 15, 2007 |
| A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word |
| 7206231 |
System for programming non-volatile memory with self-adjusting maximum program loop |
April 17, 2007 |
| The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elem |
| 7170788 |
Last-first mode and apparatus for programming of non-volatile memory with reduced program distur |
January 30, 2007 |
| A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience reduced boosting benefits due to their word line location. To achieve this result, a word |
| 7161836 |
Method for programming non-volatile memory with self-adjusting maximum program loop |
January 9, 2007 |
| The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elem |
| 7023737 |
System for programming non-volatile memory with self-adjusting maximum program loop |
April 4, 2006 |
| The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elem |
| 7009889 |
Comprehensive erase verification for non-volatile memory |
March 7, 2006 |
| Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to |
