| Patent Number |
Title Of Patent |
Date Issued |
| 6828615 |
Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory |
December 7, 2004 |
| A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that req |
| 6770954 |
Semiconductor device with SI-GE layer-containing low resistance, tunable contact |
August 3, 2004 |
| The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si.sub.x Ge.sub.1-x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The |
| 6566190 |
Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory |
May 20, 2003 |
| A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that req |
| 6511905 |
Semiconductor device with Si-Ge layer-containing low resistance, tunable contact |
January 28, 2003 |
| The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si.sub.x Ge.sub.1-x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The |
